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![David Wu](/assets/img/avatar_default.png)
Use this driver to fit all Rockchip SOCs and to support the desired pinctrl configuration via DTS. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
216 lines
4.4 KiB
C
216 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <syscon.h>
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#include "pinctrl-rockchip.h"
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static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
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{
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/* pwm0-0 */
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.bank_num = 0,
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.pin = 26,
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.func = 1,
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.route_offset = 0x50,
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.route_val = BIT(16),
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}, {
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/* pwm0-1 */
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.bank_num = 3,
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.pin = 21,
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.func = 1,
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.route_offset = 0x50,
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.route_val = BIT(16) | BIT(0),
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}, {
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/* pwm1-0 */
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.bank_num = 0,
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.pin = 27,
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.func = 1,
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.route_offset = 0x50,
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.route_val = BIT(16 + 1),
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}, {
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/* pwm1-1 */
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.bank_num = 0,
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.pin = 30,
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.func = 2,
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.route_offset = 0x50,
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.route_val = BIT(16 + 1) | BIT(1),
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}, {
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/* pwm2-0 */
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.bank_num = 0,
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.pin = 28,
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.func = 1,
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.route_offset = 0x50,
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.route_val = BIT(16 + 2),
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}, {
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/* pwm2-1 */
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.bank_num = 1,
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.pin = 12,
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.func = 2,
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.route_offset = 0x50,
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.route_val = BIT(16 + 2) | BIT(2),
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}, {
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/* pwm3-0 */
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.bank_num = 3,
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.pin = 26,
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.func = 1,
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.route_offset = 0x50,
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.route_val = BIT(16 + 3),
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}, {
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/* pwm3-1 */
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.bank_num = 1,
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.pin = 11,
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.func = 2,
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.route_offset = 0x50,
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.route_val = BIT(16 + 3) | BIT(3),
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}, {
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/* sdio-0_d0 */
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.bank_num = 1,
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.pin = 1,
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.func = 1,
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.route_offset = 0x50,
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.route_val = BIT(16 + 4),
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}, {
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/* sdio-1_d0 */
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.bank_num = 3,
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.pin = 2,
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.func = 1,
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.route_offset = 0x50,
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.route_val = BIT(16 + 4) | BIT(4),
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}, {
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/* spi-0_rx */
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.bank_num = 0,
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.pin = 13,
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.func = 2,
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.route_offset = 0x50,
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.route_val = BIT(16 + 5),
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}, {
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/* spi-1_rx */
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.bank_num = 2,
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.pin = 0,
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.func = 2,
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.route_offset = 0x50,
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.route_val = BIT(16 + 5) | BIT(5),
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}, {
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/* emmc-0_cmd */
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.bank_num = 1,
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.pin = 22,
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.func = 2,
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.route_offset = 0x50,
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.route_val = BIT(16 + 7),
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}, {
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/* emmc-1_cmd */
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.bank_num = 2,
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.pin = 4,
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.func = 2,
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.route_offset = 0x50,
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.route_val = BIT(16 + 7) | BIT(7),
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}, {
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/* uart2-0_rx */
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.bank_num = 1,
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.pin = 19,
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.func = 2,
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.route_offset = 0x50,
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.route_val = BIT(16 + 8),
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}, {
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/* uart2-1_rx */
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.bank_num = 1,
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.pin = 10,
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.func = 2,
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.route_offset = 0x50,
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.route_val = BIT(16 + 8) | BIT(8),
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}, {
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/* uart1-0_rx */
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.bank_num = 1,
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.pin = 10,
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.func = 1,
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.route_offset = 0x50,
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.route_val = BIT(16 + 11),
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}, {
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/* uart1-1_rx */
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.bank_num = 3,
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.pin = 13,
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.func = 1,
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.route_offset = 0x50,
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.route_val = BIT(16 + 11) | BIT(11),
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},
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};
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#define RK3228_PULL_OFFSET 0x100
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static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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*regmap = priv->regmap_base;
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*reg = RK3228_PULL_OFFSET;
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*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
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*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
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*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
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*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
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}
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#define RK3228_DRV_GRF_OFFSET 0x200
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static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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*regmap = priv->regmap_base;
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*reg = RK3228_DRV_GRF_OFFSET;
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*reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
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*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
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*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
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*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
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}
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static struct rockchip_pin_bank rk3228_pin_banks[] = {
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PIN_BANK(0, 32, "gpio0"),
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PIN_BANK(1, 32, "gpio1"),
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PIN_BANK(2, 32, "gpio2"),
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PIN_BANK(3, 32, "gpio3"),
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};
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static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
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.pin_banks = rk3228_pin_banks,
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.nr_banks = ARRAY_SIZE(rk3228_pin_banks),
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.label = "RK3228-GPIO",
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.type = RK3288,
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.grf_mux_offset = 0x0,
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.iomux_routes = rk3228_mux_route_data,
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.niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
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.pull_calc_reg = rk3228_calc_pull_reg_and_bit,
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.drv_calc_reg = rk3228_calc_drv_reg_and_bit,
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};
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static const struct udevice_id rk3228_pinctrl_ids[] = {
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{
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.compatible = "rockchip,rk3228-pinctrl",
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.data = (ulong)&rk3228_pin_ctrl
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},
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{ }
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};
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U_BOOT_DRIVER(pinctrl_rk3228) = {
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.name = "rockchip_rk3228_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = rk3228_pinctrl_ids,
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.priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
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.ops = &rockchip_pinctrl_ops,
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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.bind = dm_scan_fdt_dev,
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#endif
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.probe = rockchip_pinctrl_probe,
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};
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