mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-29 22:33:44 +09:00
e895a4b06f
This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detected. Unfortunately this involves changing a lot of places in the code. I have not changed behvaiour to return an error where one is not currently returned, to avoid unexpected breakage. Eventually it would be nice to allow boards to register functions to be called to update the device tree. This would avoid all the many functions to do this. However it's not clear yet if this should be done using driver model or with a linker list. This work is left for later. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
273 lines
6.6 KiB
C
273 lines
6.6 KiB
C
/*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*
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* Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
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* Author: Markus Niebel <markus.niebel@tq-group.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/errno.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <common.h>
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#include <fsl_esdhc.h>
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#include <libfdt.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <power/pfuze100_pmic.h>
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#include <power/pmic.h>
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#include "tqma6_bb.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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return 0;
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}
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static const uint16_t tqma6_emmc_dsr = 0x0100;
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/* eMMC on USDHCI3 always present */
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static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
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NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL),
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/* eMMC reset */
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NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL),
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};
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/*
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* According to board_mmc_init() the following map is done:
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* (U-boot device node) (Physical Port)
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* mmc0 eMMC (SD3) on TQMa6
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* mmc1 .. n optional slots used on baseboard
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*/
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struct fsl_esdhc_cfg tqma6_usdhc_cfg = {
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.esdhc_base = USDHC3_BASE_ADDR,
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.max_bus_width = 8,
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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if (cfg->esdhc_base == USDHC3_BASE_ADDR)
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/* eMMC/uSDHC3 is always present */
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ret = 1;
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else
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ret = tqma6_bb_board_mmc_getcd(mmc);
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return ret;
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}
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int board_mmc_getwp(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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if (cfg->esdhc_base == USDHC3_BASE_ADDR)
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/* eMMC/uSDHC3 is always present */
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ret = 0;
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else
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ret = tqma6_bb_board_mmc_getwp(mmc);
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads,
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ARRAY_SIZE(tqma6_usdhc3_pads));
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tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) {
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puts("Warning: failed to initialize eMMC dev\n");
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} else {
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struct mmc *mmc = find_mmc_device(0);
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if (mmc)
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mmc_set_dsr(mmc, tqma6_emmc_dsr);
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}
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tqma6_bb_board_mmc_init(bis);
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return 0;
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}
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static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
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/* SS1 */
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NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
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NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
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};
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#define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19)
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static unsigned const tqma6_ecspi1_cs[] = {
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TQMA6_SF_CS_GPIO,
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};
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static void tqma6_iomuxc_spi(void)
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{
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unsigned i;
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for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
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gpio_direction_output(tqma6_ecspi1_cs[i], 1);
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imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
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ARRAY_SIZE(tqma6_ecspi1_pads));
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}
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int board_spi_cs_gpio(unsigned bus, unsigned cs)
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{
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return ((bus == CONFIG_SF_DEFAULT_BUS) &&
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(cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
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}
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static struct i2c_pads_info tqma6_i2c3_pads = {
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/* I2C3: on board LM75, M24C64, */
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.scl = {
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.i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL,
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I2C_PAD_CTRL),
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.gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05,
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I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(1, 5)
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},
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.sda = {
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.i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA,
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I2C_PAD_CTRL),
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.gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06,
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I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(1, 6)
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}
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};
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static void tqma6_setup_i2c(void)
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{
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/* use logical index for bus, e.g. I2C1 -> 0 */
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setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
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}
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int board_early_init_f(void)
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{
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return tqma6_bb_board_early_init_f();
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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tqma6_iomuxc_spi();
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tqma6_setup_i2c();
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tqma6_bb_board_init();
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return 0;
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}
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static const char *tqma6_get_boardname(void)
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{
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u32 cpurev = get_cpu_rev();
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switch ((cpurev & 0xFF000) >> 12) {
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case MXC_CPU_MX6SOLO:
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return "TQMa6S";
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break;
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case MXC_CPU_MX6DL:
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return "TQMa6DL";
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break;
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case MXC_CPU_MX6D:
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return "TQMa6D";
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break;
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case MXC_CPU_MX6Q:
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return "TQMa6Q";
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break;
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default:
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return "??";
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};
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}
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int board_late_init(void)
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{
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struct pmic *p;
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u32 reg;
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setenv("board_name", tqma6_get_boardname());
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/*
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* configure PFUZE100 PMIC:
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* TODO: should go to power_init_board if bus switching is
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* fixed in generic power code
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*/
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power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
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p = pmic_get("PFUZE100");
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if (p && !pmic_probe(p)) {
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pmic_reg_read(p, PFUZE100_DEVICEID, ®);
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printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
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}
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tqma6_bb_board_late_init();
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return 0;
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}
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int checkboard(void)
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{
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printf("Board: %s on a %s\n", tqma6_get_boardname(),
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tqma6_bb_get_boardname());
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return 0;
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}
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/*
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* Device Tree Support
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*/
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#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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/* bring in eMMC dsr settings */
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do_fixup_by_path_u32(blob,
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"/soc/aips-bus@02100000/usdhc@02198000",
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"dsr", tqma6_emmc_dsr, 2);
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tqma6_bb_ft_board_setup(blob, bd);
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return 0;
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}
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#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
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