mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-08 04:06:15 +09:00
c978b52410
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
25 lines
480 B
C
25 lines
480 B
C
/*
|
|
* Copyright (C) 2009 Tensilica Inc.
|
|
* Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#ifndef _ASM_CONFIG_H_
|
|
#define _ASM_CONFIG_H_
|
|
|
|
#include <asm/arch/core.h>
|
|
|
|
#define CONFIG_LMB
|
|
|
|
/*
|
|
* Make boot parameters available in the MMUv2 virtual memory layout by
|
|
* restricting used physical memory to the first 128MB.
|
|
*/
|
|
#if XCHAL_HAVE_PTP_MMU
|
|
#define CONFIG_VERY_BIG_RAM
|
|
#define CONFIG_MAX_MEM_MAPPED (128 << 20)
|
|
#endif
|
|
|
|
#endif
|