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https://github.com/brain-hackers/u-boot-brain
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93b283d49f
Four different boards had different options for enabling cache that were virtually all the same. This consolidates these common functions into arch/arm/cpu/arm926ejs/cache.c This also has the positive side-effect of enabling cache on the Davinci (da850) boards. Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Add mach-at91 to the list of consolidations] Signed-off-by: Tom Rini <trini@konsulko.com>
91 lines
1.7 KiB
C
91 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2011
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* Ilya Yanok, EmCraft Systems
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*/
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#include <linux/types.h>
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#include <common.h>
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#ifndef CONFIG_SYS_DCACHE_OFF
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void invalidate_dcache_all(void)
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{
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asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
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}
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void flush_dcache_all(void)
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{
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asm volatile(
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"0:"
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"mrc p15, 0, r15, c7, c14, 3\n"
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"bne 0b\n"
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"mcr p15, 0, %0, c7, c10, 4\n"
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: : "r"(0) : "memory"
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);
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}
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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if (!check_cache_range(start, stop))
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return;
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while (start < stop) {
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asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
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start += CONFIG_SYS_CACHELINE_SIZE;
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}
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}
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void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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if (!check_cache_range(start, stop))
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return;
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while (start < stop) {
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asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start));
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start += CONFIG_SYS_CACHELINE_SIZE;
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}
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asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
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}
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#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
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void invalidate_dcache_all(void)
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{
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}
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void flush_dcache_all(void)
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{
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}
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#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
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/*
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* Stub implementations for l2 cache operations
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*/
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__weak void l2_cache_disable(void) {}
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#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
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__weak void invalidate_l2_cache(void) {}
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#endif
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#ifndef CONFIG_SYS_ICACHE_OFF
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/* Invalidate entire I-cache and branch predictor array */
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void invalidate_icache_all(void)
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{
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unsigned long i = 0;
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asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
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}
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#else
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void invalidate_icache_all(void) {}
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#endif
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void enable_caches(void)
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{
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#ifndef CONFIG_SYS_ICACHE_OFF
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icache_enable();
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#endif
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#ifndef CONFIG_SYS_DCACHE_OFF
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dcache_enable();
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#endif
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}
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