mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 14:16:17 +09:00
e82024def6
MIO34 is connected to POWER_KILL signal. When MIO configuration is done in psu_init() and this pin is assigned to PMU but PMU configuration is not loaded yet. PMU gpio output is high that means board is powered off immediately. The patch is fixing this sequence that MIO34 stays assing to ps gpio IP. PMU config is loaded in SPL and then pin assigned to PMU through psu_post_config_data(). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
132 lines
2.7 KiB
C
132 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 - 2016 Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <init.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/spl.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/psu_init_gpl.h>
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#include <asm/arch/sys_proto.h>
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void board_init_f(ulong dummy)
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{
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board_early_init_f();
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board_early_init_r();
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#ifdef CONFIG_DEBUG_UART
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/* Uart debug for sure */
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debug_uart_init();
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puts("Debug uart enabled\n"); /* or printch() */
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#endif
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/* Delay is required for clocks to be propagated */
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udelay(1000000);
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}
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static void ps_mode_reset(ulong mode)
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{
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writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
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&crlapb_base->boot_pin_ctrl);
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udelay(5);
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writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
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mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
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&crlapb_base->boot_pin_ctrl);
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}
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/*
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* Set default PS_MODE1 which is used for USB ULPI phy reset
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* Also other resets can be connected to this certain pin
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*/
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#ifndef MODE_RESET
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# define MODE_RESET PS_MODE1
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#endif
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#ifdef CONFIG_SPL_BOARD_INIT
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void spl_board_init(void)
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{
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preloader_console_init();
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ps_mode_reset(MODE_RESET);
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board_init();
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psu_post_config_data();
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}
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#endif
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u32 spl_boot_device(void)
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{
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u32 reg = 0;
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u8 bootmode;
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#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
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/* Change default boot mode at run-time */
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writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
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&crlapb_base->boot_mode);
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#endif
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reg = readl(&crlapb_base->boot_mode);
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if (reg >> BOOT_MODE_ALT_SHIFT)
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reg >>= BOOT_MODE_ALT_SHIFT;
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bootmode = reg & BOOT_MODES_MASK;
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switch (bootmode) {
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case JTAG_MODE:
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return BOOT_DEVICE_RAM;
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#ifdef CONFIG_SPL_MMC_SUPPORT
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case SD_MODE1:
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case SD1_LSHFT_MODE: /* not working on silicon v1 */
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/* if both controllers enabled, then these two are the second controller */
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#ifdef CONFIG_SPL_ZYNQMP_TWO_SDHCI
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return BOOT_DEVICE_MMC2;
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/* else, fall through, the one SDHCI controller that is enabled is number 1 */
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#endif
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case SD_MODE:
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case EMMC_MODE:
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return BOOT_DEVICE_MMC1;
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#endif
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#ifdef CONFIG_SPL_DFU
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case USB_MODE:
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return BOOT_DEVICE_DFU;
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#endif
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#ifdef CONFIG_SPL_SATA_SUPPORT
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case SW_SATA_MODE:
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return BOOT_DEVICE_SATA;
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#endif
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#ifdef CONFIG_SPL_SPI_SUPPORT
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case QSPI_MODE_24BIT:
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case QSPI_MODE_32BIT:
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return BOOT_DEVICE_SPI;
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#endif
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default:
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printf("Invalid Boot Mode:0x%x\n", bootmode);
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break;
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}
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return 0;
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}
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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handoff_setup();
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return 0;
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}
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#endif
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* Just empty function now - can't decide what to choose */
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debug("%s: %s\n", __func__, name);
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return 0;
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}
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#endif
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