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https://github.com/brain-hackers/u-boot-brain
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4f6c810106
When doing the AT91CAP9/AT91SAM9 port, a number of header files were copied from the Linux kernel sources. This patch explicitly specifies this origin for all the copied headers, and for those missing copyright information, adds it. Additionaly, the header file 'at91sam926x_mc.h' has been superceeded in the latest kernel sources by 'at91sam9_smc.h'. The copyright information has been confirmed by the AT91 Linux kernel maintainer, Andrew Victor <avictor.za@gmail.com>. Signed-off-by: Stelian Pop <stelian@popies.net> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
278 lines
8.0 KiB
C
278 lines
8.0 KiB
C
/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian.pop@leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/at91cap9.h>
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#include <asm/arch/at91cap9_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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#include <net.h>
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#endif
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#define MP_BLOCK_3_BASE 0xFDF00000
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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static void at91cap9_serial_hw_init(void)
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{
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#ifdef CONFIG_USART0
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at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */
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at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
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#endif
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#ifdef CONFIG_USART1
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at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
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at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
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#endif
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#ifdef CONFIG_USART2
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at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
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at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
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#endif
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#ifdef CONFIG_USART3 /* DBGU */
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at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
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at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
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#endif
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}
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static void at91cap9_nor_hw_init(void)
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{
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unsigned long csa;
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/* Ensure EBI supply is 3.3V */
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csa = at91_sys_read(AT91_MATRIX_EBICSA);
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at91_sys_write(AT91_MATRIX_EBICSA,
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csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
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/* Configure SMC CS0 for parallel flash */
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at91_sys_write(AT91_SMC_SETUP(0),
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AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
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AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
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at91_sys_write(AT91_SMC_PULSE(0),
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AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
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AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
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at91_sys_write(AT91_SMC_CYCLE(0),
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AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
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at91_sys_write(AT91_SMC_MODE(0),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
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AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
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}
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#ifdef CONFIG_CMD_NAND
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static void at91cap9_nand_hw_init(void)
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{
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unsigned long csa;
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBICSA);
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at91_sys_write(AT91_MATRIX_EBICSA,
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csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
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AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
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/* Configure SMC CS3 for NAND/SmartMedia */
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
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AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
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AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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AT91_SMC_DBW_8 | AT91_SMC_TDF_(1));
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at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
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/* RDY/BSY is not connected */
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/* Enable NandFlash */
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at91_set_gpio_output(AT91_PIN_PD15, 1);
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}
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#endif
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#ifdef CONFIG_HAS_DATAFLASH
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static void at91cap9_spi_hw_init(void)
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{
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at91_set_B_periph(AT91_PIN_PA5, 0); /* SPI0_NPCS0 */
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at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
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at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
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at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0);
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}
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#endif
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#ifdef CONFIG_MACB
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static void at91cap9_macb_hw_init(void)
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{
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC);
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/*
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* Disable pull-up on:
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* RXDV (PB22) => PHY normal mode (not Test mode)
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* ERX0 (PB25) => PHY ADDR0
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* ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
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*
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* PHY has internal pull-down
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*/
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writel(pin_to_mask(AT91_PIN_PB22) |
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pin_to_mask(AT91_PIN_PB25) |
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pin_to_mask(AT91_PIN_PB26),
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pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
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/* Need to reset PHY -> 500ms reset */
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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AT91_RSTC_ERSTL | (0x0D << 8) |
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AT91_RSTC_URSTEN);
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at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
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/* Wait for end hardware reset */
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while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
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/* Re-enable pull-up */
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writel(pin_to_mask(AT91_PIN_PB22) |
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pin_to_mask(AT91_PIN_PB25) |
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pin_to_mask(AT91_PIN_PB26),
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pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
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at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */
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at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */
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at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */
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at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */
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at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */
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at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */
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at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */
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at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */
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at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */
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at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */
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#ifndef CONFIG_RMII
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at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */
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at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
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at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
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at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
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at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
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at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
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at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
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at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
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#endif
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/* Unlock EMAC, 3 0 2 1 sequence */
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#define MP_MAC_KEY0 0x5969cb2a
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#define MP_MAC_KEY1 0xb4a1872e
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#define MP_MAC_KEY2 0x05683fbc
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#define MP_MAC_KEY3 0x3634fba4
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#define UNLOCK_MAC 0x00000008
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writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c);
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writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30);
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writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38);
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writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34);
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writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40);
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}
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#endif
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#ifdef CONFIG_USB_OHCI_NEW
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static void at91cap9_uhp_hw_init(void)
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{
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/* Unlock USB OHCI, 3 2 0 1 sequence */
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#define MP_OHCI_KEY0 0x896c11ca
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#define MP_OHCI_KEY1 0x68ebca21
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#define MP_OHCI_KEY2 0x4823efbc
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#define MP_OHCI_KEY3 0x8651aae4
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#define UNLOCK_OHCI 0x00000010
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writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c);
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writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38);
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writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30);
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writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34);
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writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40);
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}
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#endif
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int board_init(void)
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{
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/* Enable Ctrlc */
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console_init_f();
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/* arch number of AT91CAP9ADK-Board */
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gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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at91cap9_serial_hw_init();
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at91cap9_nor_hw_init();
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#ifdef CONFIG_CMD_NAND
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at91cap9_nand_hw_init();
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#endif
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#ifdef CONFIG_HAS_DATAFLASH
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at91cap9_spi_hw_init();
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#endif
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#ifdef CONFIG_MACB
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at91cap9_macb_hw_init();
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#endif
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#ifdef CONFIG_USB_OHCI_NEW
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at91cap9_uhp_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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void reset_phy(void)
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{
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#ifdef CONFIG_MACB
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/*
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* Initialize ethernet HW addr prior to starting Linux,
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* needed for nfsroot
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*/
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eth_init(gd->bd);
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#endif
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}
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#endif
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