mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
e80dac0ab8
Synopsys HSDK clock controller generates and supplies clocks to various controllers and peripherals within the SoC. Each clock has assigned identifier and client device tree nodes can use this identifier to specify the clock which they consume. All available clocks are defined as preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device tree sources. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
36 lines
1.1 KiB
Plaintext
36 lines
1.1 KiB
Plaintext
* Synopsys HSDK clock generation unit
|
|
|
|
The Synopsys HSDK clock controller generates and supplies clock to various
|
|
controllers and peripherals within the SoC.
|
|
|
|
Required Properties:
|
|
|
|
- compatible: should be "snps,hsdk-cgu-clock"
|
|
- reg: the pair of physical base address and length of clock generation unit
|
|
memory mapped region and creg arc core divider memory mapped region.
|
|
- #clock-cells: should be 1.
|
|
|
|
Each clock is assigned an identifier and client nodes can use this identifier
|
|
to specify the clock which they consume. All available clocks are defined as
|
|
preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h headers and can be
|
|
used in device tree sources.
|
|
|
|
Example: Clock controller node:
|
|
|
|
cgu_clk: cgu-clk@f0000000 {
|
|
compatible = "snps,hsdk-cgu-clock";
|
|
reg = <0xf0000000 0x1000>, <0xf00014B8 0x4>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
Example: UART controller node that consumes the clock generated by the clock
|
|
controller:
|
|
|
|
uart0: serial0@f0005000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0xf0005000 0x1000>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&cgu_clk CLK_SYS_UART_REF>;
|
|
};
|