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https://github.com/brain-hackers/u-boot-brain
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ae4c81e942
Move (and rename) the following CONFIG options to Kconfig:
CONFIG_EXYNOS_DWMMC (renamed to CONFIG_MMC_DW_EXYNOS)
CONFIG_HIKEY_DWMMC (renamed to CONFIG_MMC_DW_K3)
CONFIG_SOCFPGA_DWMMC (renamed to CONFIG_MMC_DW_SOCFPGA)
The "HIKEY" is a board name, so it is not suitable for the MMC
controller name. I am following the name used in Linux.
This commit was generated as follows:
[1] Rename the config options with the following command:
find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \
-type f -print | xargs sed -i -e '
s/CONFIG_EXYNOS_DWMMC/CONFIG_MMC_DW_EXYNOS/g
s/CONFIG_HIKEY_DWMMC/CONFIG_MMC_DW_K3/g
s/CONFIG_SOCFPGA_DWMMC/CONFIG_MMC_DW_SOCFPGA/g
'
[2] Commit the changes
[3] Create the entries in drivers/mmc/Kconfig
(with default y for EXYNOS and SOCFPGA)
[4] Run the following:
tools/moveconfig.py -y -r HEAD MMC_DW_EXYNOS MMC_DW_K3 MMC_DW_SOCFPGA
[5] Sort and align drivers/mmc/Makefile for readability
[6] Clean-up doc/README.socfpga by hand
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
22 lines
693 B
Plaintext
22 lines
693 B
Plaintext
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--------------------------------------------
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SOCFPGA Documentation for U-Boot and SPL
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--------------------------------------------
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This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore
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based SOCFPGA. To know more about the hardware itself, please refer to
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www.altera.com.
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--------------------------------------------
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socfpga_dw_mmc
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--------------------------------------------
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Here are macro and detailed configuration required to enable DesignWare SDMMC
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controller support within SOCFPGA
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#define CONFIG_GENERIC_MMC
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-> Enable the generic MMC driver
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#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
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-> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
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