412 lines
11 KiB
C
412 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2018
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
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*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux-vf610.h>
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#include <asm/arch/ddrmc-vf610.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <env.h>
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#include <led.h>
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#include <miiphy.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct ddrmc_cr_setting pcm052_cr_settings[] = {
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/* not in the datasheets, but in the original code */
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{ 0x00002000, 105 },
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{ 0x00000020, 110 },
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/* AXI */
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{ DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), 117 },
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{ DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
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{ DDRMC_CR120_AXI0_PRI1_RPRI(2) |
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DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
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{ DDRMC_CR121_AXI0_PRI3_RPRI(2) |
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DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
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{ DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
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DDRMC_CR122_AXI0_PRIRLX(100), 122 },
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{ DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
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DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
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{ DDRMC_CR124_AXI1_PRIRLX(100), 124 },
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{ DDRMC_CR126_PHY_RDLAT(11), 126 },
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{ DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), 132 },
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{ DDRMC_CR137_PHYCTL_DL(2), 137 },
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{ DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
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DDRMC_CR139_PHY_WRLV_DLL(3) |
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DDRMC_CR139_PHY_WRLV_EN(3), 139 },
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{ DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
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DDRMC_CR154_PAD_ZQ_MODE(1) |
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DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
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DDRMC_CR154_PAD_ZQ_HW_FOR(0), 154 },
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{ DDRMC_CR155_PAD_ODT_BYTE1(5) | DDRMC_CR155_PAD_ODT_BYTE0(5), 155 },
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{ DDRMC_CR158_TWR(6), 158 },
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{ DDRMC_CR161_ODT_EN(0) | DDRMC_CR161_TODTH_RD(0) |
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DDRMC_CR161_TODTH_WR(6), 161 },
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/* end marker */
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{ 0, -1 }
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};
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/* PHY settings -- most of them differ from default in imx-regs.h */
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#define PCM052_DDRMC_PHY_DQ_TIMING 0x00002213
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#define PCM052_DDRMC_PHY_CTRL 0x00290000
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#define PCM052_DDRMC_PHY_SLAVE_CTRL 0x00002c00
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#define PCM052_DDRMC_PHY_PROC_PAD_ODT 0x00010020
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static struct ddrmc_phy_setting pcm052_phy_settings[] = {
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{ PCM052_DDRMC_PHY_DQ_TIMING, 0 },
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{ PCM052_DDRMC_PHY_DQ_TIMING, 16 },
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{ PCM052_DDRMC_PHY_DQ_TIMING, 32 },
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{ PCM052_DDRMC_PHY_DQ_TIMING, 48 },
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{ DDRMC_PHY_DQS_TIMING, 1 },
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{ DDRMC_PHY_DQS_TIMING, 17 },
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{ DDRMC_PHY_DQS_TIMING, 33 },
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{ DDRMC_PHY_DQS_TIMING, 49 },
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{ PCM052_DDRMC_PHY_CTRL, 2 },
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{ PCM052_DDRMC_PHY_CTRL, 18 },
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{ PCM052_DDRMC_PHY_CTRL, 34 },
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{ DDRMC_PHY_MASTER_CTRL, 3 },
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{ DDRMC_PHY_MASTER_CTRL, 19 },
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{ DDRMC_PHY_MASTER_CTRL, 35 },
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{ PCM052_DDRMC_PHY_SLAVE_CTRL, 4 },
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{ PCM052_DDRMC_PHY_SLAVE_CTRL, 20 },
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{ PCM052_DDRMC_PHY_SLAVE_CTRL, 36 },
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{ DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
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{ PCM052_DDRMC_PHY_PROC_PAD_ODT, 52 },
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/* end marker */
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{ 0, -1 }
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};
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int dram_init(void)
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{
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#if defined(CONFIG_TARGET_PCM052)
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static const struct ddr3_jedec_timings pcm052_ddr_timings = {
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.tinit = 5,
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.trst_pwron = 80000,
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.cke_inactive = 200000,
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.wrlat = 5,
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.caslat_lin = 12,
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.trc = 6,
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.trrd = 4,
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.tccd = 4,
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.tbst_int_interval = 4,
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.tfaw = 18,
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.trp = 6,
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.twtr = 4,
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.tras_min = 15,
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.tmrd = 4,
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.trtp = 4,
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.tras_max = 14040,
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.tmod = 12,
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.tckesr = 4,
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.tcke = 3,
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.trcd_int = 6,
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.tras_lockout = 1,
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.tdal = 10,
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.bstlen = 3,
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.tdll = 512,
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.trp_ab = 6,
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.tref = 1542,
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.trfc = 64,
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.tref_int = 5,
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.tpdex = 3,
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.txpdll = 10,
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.txsnr = 68,
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.txsr = 506,
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.cksrx = 5,
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.cksre = 5,
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.freq_chg_en = 1,
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.zqcl = 256,
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.zqinit = 512,
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.zqcs = 64,
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.ref_per_zq = 64,
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.zqcs_rotate = 1,
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.aprebit = 10,
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.cmd_age_cnt = 255,
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.age_cnt = 255,
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.q_fullness = 0,
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.odt_rd_mapcs0 = 1,
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.odt_wr_mapcs0 = 1,
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.wlmrd = 40,
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.wldqsen = 25,
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};
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const int row_diff = 2;
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#elif defined(CONFIG_TARGET_BK4R1)
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static const struct ddr3_jedec_timings pcm052_ddr_timings = {
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.tinit = 5,
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.trst_pwron = 80000,
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.cke_inactive = 200000,
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.wrlat = 5,
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.caslat_lin = 12,
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.trc = 6,
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.trrd = 4,
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.tccd = 4,
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.tbst_int_interval = 0,
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.tfaw = 16,
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.trp = 6,
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.twtr = 4,
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.tras_min = 15,
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.tmrd = 4,
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.trtp = 4,
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.tras_max = 28080,
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.tmod = 12,
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.tckesr = 4,
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.tcke = 3,
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.trcd_int = 6,
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.tras_lockout = 1,
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.tdal = 12,
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.bstlen = 3,
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.tdll = 512,
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.trp_ab = 6,
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.tref = 3120,
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.trfc = 104,
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.tref_int = 0,
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.tpdex = 3,
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.txpdll = 10,
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.txsnr = 108,
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.txsr = 512,
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.cksrx = 5,
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.cksre = 5,
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.freq_chg_en = 1,
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.zqcl = 256,
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.zqinit = 512,
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.zqcs = 64,
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.ref_per_zq = 64,
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.zqcs_rotate = 1,
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.aprebit = 10,
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.cmd_age_cnt = 255,
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.age_cnt = 255,
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.q_fullness = 0,
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.odt_rd_mapcs0 = 1,
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.odt_wr_mapcs0 = 1,
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.wlmrd = 40,
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.wldqsen = 25,
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};
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const int row_diff = 1;
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#else /* Unknown PCM052 variant */
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#error DDR characteristics undefined for this target. Please define them.
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#endif
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ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
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pcm052_phy_settings, 1, row_diff);
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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return 0;
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}
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static void clock_init(void)
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{
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struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
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struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
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clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
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CCM_CCGR0_UART1_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
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CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
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CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
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CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
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CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
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CCM_CCGR2_QSPI0_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
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CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
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CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
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CCM_CCGR4_GPC_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
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CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
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CCM_CCGR7_SDHC1_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
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CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
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CCM_CCGR10_NFC_CTRL_MASK);
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clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
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ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
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clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
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ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
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clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
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CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
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clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
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CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
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CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
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CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
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CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
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CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
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CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
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clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
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CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
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CCM_CACRR_ARM_CLK_DIV(0));
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clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
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CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
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CCM_CSCMR1_QSPI0_CLK_SEL(3) |
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CCM_CSCMR1_NFC_CLK_SEL(0));
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clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
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CCM_CSCDR1_RMII_CLK_EN);
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clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
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CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
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CCM_CSCDR2_NFC_EN);
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clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
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CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
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CCM_CSCDR3_QSPI0_X2_DIV(1) |
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CCM_CSCDR3_QSPI0_X4_DIV(3) |
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CCM_CSCDR3_NFC_PRE_DIV(5));
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clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
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CCM_CSCMR2_RMII_CLK_SEL(0));
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}
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static void mscm_init(void)
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{
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struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
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int i;
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for (i = 0; i < MSCM_IRSPRC_NUM; i++)
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writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
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}
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int board_early_init_f(void)
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{
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clock_init();
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mscm_init();
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return 0;
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}
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int board_init(void)
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{
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struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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/*
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* Enable external 32K Oscillator
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*
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* The internal clock experiences significant drift
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* so we must use the external oscillator in order
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* to maintain correct time in the hwclock
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*/
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setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
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return 0;
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}
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#ifdef CONFIG_TARGET_BK4R1
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void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[4];
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struct fuse_bank4_regs *fuse =
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(struct fuse_bank4_regs *)bank->fuse_regs;
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u32 value;
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/*
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* BK4 has different layout of stored MAC address
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* than one used in imx_get_mac_from_fuse() @ generic.c
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*/
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switch (dev_id) {
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case 0:
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value = readl(&fuse->mac_addr1);
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mac[0] = value >> 8;
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mac[1] = value;
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value = readl(&fuse->mac_addr0);
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mac[2] = value >> 24;
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mac[3] = value >> 16;
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mac[4] = value >> 8;
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mac[5] = value;
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break;
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case 1:
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value = readl(&fuse->mac_addr2);
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mac[0] = value >> 24;
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mac[1] = value >> 16;
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mac[2] = value >> 8;
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mac[3] = value;
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value = readl(&fuse->mac_addr1);
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mac[4] = value >> 24;
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mac[5] = value >> 16;
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break;
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}
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}
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int board_late_init(void)
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{
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struct src *psrc = (struct src *)SRC_BASE_ADDR;
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u32 reg;
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if (IS_ENABLED(CONFIG_LED))
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led_default_state();
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/*
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* BK4r1 handle emergency/service SD card boot
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* Checking the SBMR1 register BOOTCFG1 byte:
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* NAND:
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* bit [2] - NAND data width - 16
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* bit [5] - NAND fast boot
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* bit [7] = 1 - NAND as a source of booting
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* SD card (0x64):
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* bit [4] = 0 - SD card source
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* bit [6] = 1 - SD/MMC source
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*/
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reg = readl(&psrc->sbmr1);
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if ((reg & SRC_SBMR1_BOOTCFG1_SDMMC) &&
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!(reg & SRC_SBMR1_BOOTCFG1_MMC)) {
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printf("------ SD card boot -------\n");
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env_set_default("!LVFBootloader", 0);
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env_set("bootcmd",
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"run prepare_install_bk4r1_envs; run install_bk4r1rs");
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}
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return 0;
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}
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/**
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* KSZ8081
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*/
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#define MII_KSZ8081_REFERENCE_CLOCK_SELECT 0x1f
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#define RMII_50MHz_CLOCK 0x8180
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int board_phy_config(struct phy_device *phydev)
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{
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/* Set 50 MHz reference clock */
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phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8081_REFERENCE_CLOCK_SELECT,
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RMII_50MHz_CLOCK);
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return genphy_config(phydev);
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}
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#endif /* CONFIG_TARGET_BK4R1 */
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int checkboard(void)
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{
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#ifdef CONFIG_TARGET_BK4R1
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puts("Board: BK4r1 (L333)\n");
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#else
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puts("Board: PCM-052\n");
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#endif
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return 0;
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}
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