186 lines
4.5 KiB
C
186 lines
4.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* board.c
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*
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* Board functions for Bosch Guardian
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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* Copyright (C) 2018 Robert Bosch Power Tools GmbH
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*/
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#include <common.h>
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#include <cpsw.h>
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#include <dm.h>
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#include <environment.h>
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#include <errno.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <panel.h>
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#include <power/tps65217.h>
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#include <power/tps65910.h>
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#include <spl.h>
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#include <watchdog.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = MT41K128M16JT125K_RD_DQS,
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.datawdsratio0 = MT41K128M16JT125K_WR_DQS,
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.datafwsratio0 = MT41K128M16JT125K_PHY_FIFO_WE,
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.datawrsratio0 = MT41K128M16JT125K_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = MT41K128M16JT125K_RATIO,
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.cmd0iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
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.cmd1csratio = MT41K128M16JT125K_RATIO,
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.cmd1iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
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.cmd2csratio = MT41K128M16JT125K_RATIO,
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.cmd2iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = MT41K128M16JT125K_EMIF_SDCFG,
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.ref_ctrl = MT41K128M16JT125K_EMIF_SDREF,
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.sdram_tim1 = MT41K128M16JT125K_EMIF_TIM1,
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.sdram_tim2 = MT41K128M16JT125K_EMIF_TIM2,
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.sdram_tim3 = MT41K128M16JT125K_EMIF_TIM3,
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.zq_config = MT41K128M16JT125K_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K128M16JT125K_EMIF_READ_LATENCY,
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};
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#define OSC (V_OSCK / 1000000)
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const struct dpll_params dpll_ddr = {
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400, OSC - 1, 1, -1, -1, -1, -1};
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void am33xx_spl_board_init(void)
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{
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int mpu_vdd;
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int usb_cur_lim;
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/* Get the frequency */
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dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
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if (i2c_probe(TPS65217_CHIP_PM))
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return;
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/*
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* Increase USB current limit to 1300mA or 1800mA and set
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* the MPU voltage controller as needed.
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*/
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if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
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usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
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mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
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} else {
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usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
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mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
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}
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if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
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TPS65217_POWER_PATH,
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usb_cur_lim,
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TPS65217_USB_INPUT_CUR_LIMIT_MASK))
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puts("tps65217_reg_write failure\n");
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/* Set DCDC3 (CORE) voltage to 1.125V */
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if (tps65217_voltage_update(TPS65217_DEFDCDC3,
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TPS65217_DCDC_VOLT_SEL_1125MV)) {
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puts("tps65217_voltage_update failure\n");
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return;
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}
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/* Set CORE Frequencies to OPP100 */
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do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
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/* Set DCDC2 (MPU) voltage */
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if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
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puts("tps65217_voltage_update failure\n");
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return;
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}
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/*
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* Set LDO3 to 1.8V and LDO4 to 3.3V
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*/
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if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
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TPS65217_DEFLS1,
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TPS65217_LDO_VOLTAGE_OUT_1_8,
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TPS65217_LDO_MASK))
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puts("tps65217_reg_write failure\n");
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if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
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TPS65217_DEFLS2,
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TPS65217_LDO_VOLTAGE_OUT_3_3,
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TPS65217_LDO_MASK))
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puts("tps65217_reg_write failure\n");
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/* Set MPU Frequency to what we detected now that voltages are set */
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do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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enable_i2c0_pin_mux();
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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return &dpll_ddr;
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}
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void set_uart_mux_conf(void)
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{
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enable_uart0_pin_mux();
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}
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void set_mux_conf_regs(void)
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{
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enable_board_pin_mux();
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}
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const struct ctrl_ioregs ioregs = {
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.cm0ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
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.cm1ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
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.cm2ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
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.dt0ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
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.dt1ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
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};
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void sdram_init(void)
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{
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config_ddr(400, &ioregs,
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&ddr3_data,
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&ddr3_cmd_ctrl_data,
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&ddr3_emif_reg_data, 0);
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}
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#endif
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int board_init(void)
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{
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#if defined(CONFIG_HW_WATCHDOG)
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hw_watchdog_init();
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#endif
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_NAND
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gpmc_init();
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#endif
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return 0;
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}
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