mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-29 05:18:51 +09:00
![Guillaume La Roque](/assets/img/avatar_default.png)
drive-strength-microamp is a new feature needed for G12A SoC. the default DS setting after boot is usually 500uA and it is not enough for many functions. We need to be able to set the drive strength to reliably enable things like MMC, I2C, etc ... Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
422 lines
9.7 KiB
C
422 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/pinctrl.h>
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#include <fdt_support.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <asm/gpio.h>
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#include "pinctrl-meson.h"
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DECLARE_GLOBAL_DATA_PTR;
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static const char *meson_pinctrl_dummy_name = "_dummy";
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static char pin_name[PINNAME_SIZE];
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int meson_pinctrl_get_groups_count(struct udevice *dev)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev);
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return priv->data->num_groups;
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}
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const char *meson_pinctrl_get_group_name(struct udevice *dev,
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unsigned int selector)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev);
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if (!priv->data->groups[selector].name)
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return meson_pinctrl_dummy_name;
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return priv->data->groups[selector].name;
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}
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int meson_pinctrl_get_pins_count(struct udevice *dev)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev);
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return priv->data->num_pins;
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}
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const char *meson_pinctrl_get_pin_name(struct udevice *dev,
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unsigned int selector)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev);
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if (selector > priv->data->num_pins ||
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selector > priv->data->funcs[0].num_groups)
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snprintf(pin_name, PINNAME_SIZE, "Error");
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else
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snprintf(pin_name, PINNAME_SIZE, "%s",
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priv->data->funcs[0].groups[selector]);
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return pin_name;
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}
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int meson_pinmux_get_functions_count(struct udevice *dev)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev);
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return priv->data->num_funcs;
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}
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const char *meson_pinmux_get_function_name(struct udevice *dev,
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unsigned int selector)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev);
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return priv->data->funcs[selector].name;
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}
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static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset,
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enum meson_reg_type reg_type,
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unsigned int *reg, unsigned int *bit)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev);
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struct meson_bank *bank = NULL;
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struct meson_reg_desc *desc;
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unsigned int pin;
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int i;
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pin = priv->data->pin_base + offset;
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for (i = 0; i < priv->data->num_banks; i++) {
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if (pin >= priv->data->banks[i].first &&
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pin <= priv->data->banks[i].last) {
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bank = &priv->data->banks[i];
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break;
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}
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}
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if (!bank)
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return -EINVAL;
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desc = &bank->regs[reg_type];
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*reg = desc->reg * 4;
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*bit = desc->bit + pin - bank->first;
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return 0;
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}
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int meson_gpio_get(struct udevice *dev, unsigned int offset)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev->parent);
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unsigned int reg, bit;
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int ret;
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ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_IN, ®,
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&bit);
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if (ret)
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return ret;
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return !!(readl(priv->reg_gpio + reg) & BIT(bit));
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}
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int meson_gpio_set(struct udevice *dev, unsigned int offset, int value)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev->parent);
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unsigned int reg, bit;
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int ret;
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ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_OUT, ®,
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&bit);
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if (ret)
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return ret;
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clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0);
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return 0;
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}
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int meson_gpio_get_direction(struct udevice *dev, unsigned int offset)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev->parent);
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unsigned int reg, bit, val;
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int ret;
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ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_DIR, ®,
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&bit);
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if (ret)
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return ret;
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val = readl(priv->reg_gpio + reg);
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return (val & BIT(bit)) ? GPIOF_INPUT : GPIOF_OUTPUT;
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}
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int meson_gpio_direction_input(struct udevice *dev, unsigned int offset)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev->parent);
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unsigned int reg, bit;
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int ret;
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ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_DIR, ®,
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&bit);
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if (ret)
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return ret;
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setbits_le32(priv->reg_gpio + reg, BIT(bit));
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return 0;
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}
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int meson_gpio_direction_output(struct udevice *dev,
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unsigned int offset, int value)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev->parent);
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unsigned int reg, bit;
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int ret;
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ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_DIR, ®,
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&bit);
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if (ret)
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return ret;
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clrbits_le32(priv->reg_gpio + reg, BIT(bit));
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ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_OUT, ®,
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&bit);
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if (ret)
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return ret;
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clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0);
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return 0;
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}
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static int meson_pinconf_bias_set(struct udevice *dev, unsigned int pin,
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unsigned int param)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev);
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unsigned int offset = pin - priv->data->pin_base;
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unsigned int reg, bit;
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int ret;
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ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_PULLEN, ®, &bit);
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if (ret)
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return ret;
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if (param == PIN_CONFIG_BIAS_DISABLE) {
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clrsetbits_le32(priv->reg_pullen + reg, BIT(bit), 0);
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return 0;
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}
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/* othewise, enable the bias and select level */
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clrsetbits_le32(priv->reg_pullen + reg, BIT(bit), 1);
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ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_PULL, ®, &bit);
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if (ret)
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return ret;
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clrsetbits_le32(priv->reg_pull + reg, BIT(bit),
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param == PIN_CONFIG_BIAS_PULL_UP);
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return 0;
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}
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static int meson_pinconf_drive_strength_set(struct udevice *dev,
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unsigned int pin,
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unsigned int drive_strength_ua)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev);
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unsigned int offset = pin - priv->data->pin_base;
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unsigned int reg, bit;
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unsigned int ds_val;
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int ret;
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if (!priv->reg_ds) {
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dev_err(dev, "drive-strength-microamp not supported\n");
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return -ENOTSUPP;
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}
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ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_DS, ®, &bit);
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if (ret)
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return ret;
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bit = bit << 1;
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if (drive_strength_ua <= 500) {
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ds_val = MESON_PINCONF_DRV_500UA;
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} else if (drive_strength_ua <= 2500) {
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ds_val = MESON_PINCONF_DRV_2500UA;
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} else if (drive_strength_ua <= 3000) {
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ds_val = MESON_PINCONF_DRV_3000UA;
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} else if (drive_strength_ua <= 4000) {
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ds_val = MESON_PINCONF_DRV_4000UA;
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} else {
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dev_warn(dev,
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"pin %u: invalid drive-strength-microamp : %d , default to 4mA\n",
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pin, drive_strength_ua);
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ds_val = MESON_PINCONF_DRV_4000UA;
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}
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clrsetbits_le32(priv->reg_ds + reg, 0x3 << bit, ds_val << bit);
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return 0;
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}
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int meson_pinconf_set(struct udevice *dev, unsigned int pin,
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unsigned int param, unsigned int arg)
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{
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int ret;
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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case PIN_CONFIG_BIAS_PULL_UP:
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case PIN_CONFIG_BIAS_PULL_DOWN:
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ret = meson_pinconf_bias_set(dev, pin, param);
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break;
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case PIN_CONFIG_DRIVE_STRENGTH_UA:
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ret = meson_pinconf_drive_strength_set(dev, pin, arg);
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break;
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default:
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dev_err(dev, "unsupported configuration parameter %u\n", param);
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return -EINVAL;
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}
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return ret;
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}
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int meson_pinconf_group_set(struct udevice *dev,
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unsigned int group_selector,
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unsigned int param, unsigned int arg)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev);
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struct meson_pmx_group *grp = &priv->data->groups[group_selector];
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int i, ret;
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for (i = 0; i < grp->num_pins; i++) {
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ret = meson_pinconf_set(dev, grp->pins[i], param, arg);
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if (ret)
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return ret;
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}
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return 0;
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}
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int meson_gpio_probe(struct udevice *dev)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev->parent);
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struct gpio_dev_priv *uc_priv;
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uc_priv = dev_get_uclass_priv(dev);
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uc_priv->bank_name = priv->data->name;
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uc_priv->gpio_count = priv->data->num_pins;
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return 0;
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}
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static fdt_addr_t parse_address(int offset, const char *name, int na, int ns)
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{
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int index, len = 0;
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const fdt32_t *reg;
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index = fdt_stringlist_search(gd->fdt_blob, offset, "reg-names", name);
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if (index < 0)
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return FDT_ADDR_T_NONE;
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reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
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if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns))))
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return FDT_ADDR_T_NONE;
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reg += index * (na + ns);
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return fdt_translate_address((void *)gd->fdt_blob, offset, reg);
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}
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int meson_pinctrl_probe(struct udevice *dev)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev);
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struct uclass_driver *drv;
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struct udevice *gpio_dev;
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fdt_addr_t addr;
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int node, gpio = -1, len;
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int na, ns;
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char *name;
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na = fdt_address_cells(gd->fdt_blob, dev_of_offset(dev->parent));
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if (na < 1) {
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debug("bad #address-cells\n");
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return -EINVAL;
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}
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ns = fdt_size_cells(gd->fdt_blob, dev_of_offset(dev->parent));
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if (ns < 1) {
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debug("bad #size-cells\n");
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return -EINVAL;
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}
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fdt_for_each_subnode(node, gd->fdt_blob, dev_of_offset(dev)) {
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if (fdt_getprop(gd->fdt_blob, node, "gpio-controller", &len)) {
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gpio = node;
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break;
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}
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}
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if (!gpio) {
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debug("gpio node not found\n");
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return -EINVAL;
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}
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addr = parse_address(gpio, "mux", na, ns);
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if (addr == FDT_ADDR_T_NONE) {
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debug("mux address not found\n");
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return -EINVAL;
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}
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priv->reg_mux = (void __iomem *)addr;
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addr = parse_address(gpio, "gpio", na, ns);
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if (addr == FDT_ADDR_T_NONE) {
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debug("gpio address not found\n");
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return -EINVAL;
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}
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priv->reg_gpio = (void __iomem *)addr;
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addr = parse_address(gpio, "pull", na, ns);
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/* Use gpio region if pull one is not present */
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if (addr == FDT_ADDR_T_NONE)
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priv->reg_pull = priv->reg_gpio;
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else
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priv->reg_pull = (void __iomem *)addr;
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addr = parse_address(gpio, "pull-enable", na, ns);
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/* Use pull region if pull-enable one is not present */
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if (addr == FDT_ADDR_T_NONE)
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priv->reg_pullen = priv->reg_pull;
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else
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priv->reg_pullen = (void __iomem *)addr;
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addr = parse_address(gpio, "ds", na, ns);
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/* Drive strength region is optional */
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if (addr == FDT_ADDR_T_NONE)
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priv->reg_ds = NULL;
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else
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priv->reg_ds = (void __iomem *)addr;
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priv->data = (struct meson_pinctrl_data *)dev_get_driver_data(dev);
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/* Lookup GPIO driver */
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drv = lists_uclass_lookup(UCLASS_GPIO);
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if (!drv) {
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puts("Cannot find GPIO driver\n");
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return -ENOENT;
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}
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name = calloc(1, 32);
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sprintf(name, "meson-gpio");
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/* Create child device UCLASS_GPIO and bind it */
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device_bind(dev, priv->data->gpio_driver, name, NULL, gpio, &gpio_dev);
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dev_set_of_offset(gpio_dev, gpio);
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return 0;
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}
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