mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 19:56:18 +09:00
16e369f5ec
The min/max of each depends not only on board but on CPU. Simplify by removing this rarely needed and difficult to maintain feature and just display the rails and their values. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
125 lines
2.9 KiB
C
125 lines
2.9 KiB
C
/*
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* Copyright (C) 2013 Gateworks Corporation
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*
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* Author: Tim Harvey <tharvey@gateworks.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/errno.h>
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#include <common.h>
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#include <i2c.h>
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#include <linux/ctype.h>
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#include "gsc.h"
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/*
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* The Gateworks System Controller will fail to ACK a master transaction if
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* it is busy, which can occur during its 1HZ timer tick while reading ADC's.
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* When this does occur, it will never be busy long enough to fail more than
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* 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with
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* 3 retries.
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*/
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int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
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{
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int retry = 3;
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int n = 0;
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int ret;
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while (n++ < retry) {
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ret = i2c_read(chip, addr, alen, buf, len);
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if (!ret)
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break;
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debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
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n, ret);
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if (ret != -ENODEV)
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break;
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mdelay(10);
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}
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return ret;
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}
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int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
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{
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int retry = 3;
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int n = 0;
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int ret;
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while (n++ < retry) {
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ret = i2c_write(chip, addr, alen, buf, len);
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if (!ret)
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break;
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debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
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n, ret);
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if (ret != -ENODEV)
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break;
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mdelay(10);
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}
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mdelay(100);
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return ret;
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}
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#ifdef CONFIG_CMD_GSC
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static void read_hwmon(const char *name, uint reg, uint size)
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{
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unsigned char buf[3];
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uint ui;
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printf("%-8s:", name);
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memset(buf, 0, sizeof(buf));
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if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) {
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puts("fRD\n");
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} else {
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ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
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if (ui == 0xffffff)
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puts("invalid\n");
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else
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printf("%d\n", ui);
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}
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}
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int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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const char *model = getenv("model");
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i2c_set_bus_num(0);
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read_hwmon("Temp", GSC_HWMON_TEMP, 2);
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read_hwmon("VIN", GSC_HWMON_VIN, 3);
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read_hwmon("VBATT", GSC_HWMON_VBATT, 3);
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read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3);
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read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3);
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read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3);
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read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3);
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read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3);
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read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3);
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switch (model[3]) {
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case '1': /* GW51xx */
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read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3);
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read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3);
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break;
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case '2': /* GW52xx */
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case '3': /* GW53xx */
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read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3);
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read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3);
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read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3);
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break;
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case '4': /* GW54xx */
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read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3);
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read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3);
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read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3);
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break;
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case '5': /* GW55xx */
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read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3);
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read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3);
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break;
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}
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return 0;
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}
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U_BOOT_CMD(gsc, 1, 1, do_gsc,
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"GSC test",
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""
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);
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#endif /* CONFIG_CMD_GSC */
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