mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 11:16:15 +09:00
8ca78f2c89
Previously boards used a variety of indentations, newline styles, and
colon styles for the PCI information that is printed on bootup. This
patch unifies the style to look like:
...
NAND: 1024 MiB
PCIE1: connected as Root Complex
Scanning PCI bus 01
04 01 8086 1010 0200 00
04 01 8086 1010 0200 00
03 00 10b5 8112 0604 00
02 01 10b5 8518 0604 00
02 02 10b5 8518 0604 00
08 00 1957 0040 0b20 00
07 00 10b5 8518 0604 00
09 00 10b5 8112 0604 00
07 01 10b5 8518 0604 00
07 02 10b5 8518 0604 00
06 00 10b5 8518 0604 00
02 03 10b5 8518 0604 00
01 00 10b5 8518 0604 00
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
Scanning PCI bus 0d
0d 00 1957 0040 0b20 00
PCIE2: Bus 0c - 0d
In: serial
...
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
CC: wd@denx.de
CC: sr@denx.de
CC: galak@kernel.crashing.org
491 lines
17 KiB
C
491 lines
17 KiB
C
/*
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* Copyright 2004 Freescale Semiconductor.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <ioports.h>
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#include <spd_sdram.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include "../common/cadmus.h"
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#include "../common/eeprom.h"
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#include "../common/via.h"
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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void local_bus_init(void);
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void sdram_init(void);
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
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/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
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/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
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/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
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/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
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/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
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/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
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/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
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/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
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/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
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/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
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/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
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/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
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/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
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/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
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/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
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/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
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/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
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/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
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/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
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/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
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/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
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/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
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/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
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/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
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/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
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/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
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/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
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/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
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/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
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/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
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/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
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},
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/* Port B configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
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/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
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/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
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/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
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/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
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/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
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/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
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/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
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/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
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/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
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/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
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/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
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/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
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/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
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/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
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/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
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/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
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/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
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/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
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/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
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/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
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/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
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/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
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/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
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/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
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/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
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/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
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/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
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/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
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/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
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/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
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/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
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/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
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/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
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/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
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/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
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/* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
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/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
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/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
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/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
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/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
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/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
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/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
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/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
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/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
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/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
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/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
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/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
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/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
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/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
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/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
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/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
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},
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
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/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
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/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
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/* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
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/* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
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/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
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/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
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/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
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/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
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/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
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/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
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/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
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/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
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/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
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/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
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/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
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/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
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/* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
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/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
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/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
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/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
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/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
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/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
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/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
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/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
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/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
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/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
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/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
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/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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}
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};
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int checkboard (void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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/* PCI slot in USER bits CSR[6:7] by convention. */
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uint pci_slot = get_pci_slot ();
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uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
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uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
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uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
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uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
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uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
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uint cpu_board_rev = get_cpu_board_revision ();
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printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
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get_board_version (), pci_slot);
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printf ("CPU Board Revision %d.%d (0x%04x)\n",
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MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
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MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
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printf("PCI1: %d bit, %s MHz, %s\n",
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(pci1_32) ? 32 : 64,
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(pci1_speed == 33000000) ? "33" :
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(pci1_speed == 66000000) ? "66" : "unknown",
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pci1_clk_sel ? "sync" : "async");
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if (pci_dual) {
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printf("PCI2: 32 bit, 66 MHz, %s\n",
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pci2_clk_sel ? "sync" : "async");
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} else {
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printf("PCI2: disabled\n");
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}
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/*
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* Initialize local bus.
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*/
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local_bus_init ();
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return 0;
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}
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phys_size_t
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initdram(int board_type)
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{
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long dram_size = 0;
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puts("Initializing\n");
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#if defined(CONFIG_DDR_DLL)
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{
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/*
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* Work around to stabilize DDR DLL MSYNC_IN.
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* Errata DDR9 seems to have been fixed.
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* This is now the workaround for Errata DDR11:
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* Override DLL = 1, Course Adj = 1, Tap Select = 0
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*/
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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gur->ddrdllcr = 0x81000000;
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asm("sync;isync;msync");
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udelay(200);
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}
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#endif
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dram_size = fsl_ddr_sdram();
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize and enable DDR ECC.
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*/
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ddr_enable_ecc(dram_size);
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#endif
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/*
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* SDRAM Initialization
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*/
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sdram_init();
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puts(" DDR: ");
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return dram_size;
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}
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/*
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* Initialize Local Bus
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*/
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void
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local_bus_init(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
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uint clkdiv;
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uint lbc_hz;
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sys_info_t sysinfo;
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uint temp_lbcdll;
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/*
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* Errata LBC11.
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* Fix Local Bus clock glitch when DLL is enabled.
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*
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* If localbus freq is < 66MHz, DLL bypass mode must be used.
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* If localbus freq is > 133MHz, DLL can be safely enabled.
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* Between 66 and 133, the DLL is enabled with an override workaround.
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*/
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get_sys_info(&sysinfo);
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clkdiv = lbc->lcrr & LCRR_CLKDIV;
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lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
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if (lbc_hz < 66) {
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lbc->lcrr |= 0x80000000; /* DLL Bypass */
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} else if (lbc_hz >= 133) {
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lbc->lcrr &= (~0x80000000); /* DLL Enabled */
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} else {
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lbc->lcrr &= (~0x8000000); /* DLL Enabled */
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udelay(200);
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/*
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* Sample LBC DLL ctrl reg, upshift it to set the
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* override bits.
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*/
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temp_lbcdll = gur->lbcdllcr;
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gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
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asm("sync;isync;msync");
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}
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}
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/*
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* Initialize SDRAM memory on the Local Bus.
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*/
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void
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sdram_init(void)
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{
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#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
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uint idx;
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volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
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uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
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uint cpu_board_rev;
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uint lsdmr_common;
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puts(" SDRAM: ");
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print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
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/*
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* Setup SDRAM Base and Option Registers
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*/
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set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
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set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
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lbc->lbcr = CONFIG_SYS_LBC_LBCR;
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asm("msync");
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lbc->lsrt = CONFIG_SYS_LBC_LSRT;
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lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
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asm("msync");
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/*
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* Determine which address lines to use baed on CPU board rev.
|
|
*/
|
|
cpu_board_rev = get_cpu_board_revision();
|
|
lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
|
|
if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
|
|
lsdmr_common |= LSDMR_BSMA1617;
|
|
} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
|
|
lsdmr_common |= LSDMR_BSMA1516;
|
|
} else {
|
|
/*
|
|
* Assume something unable to identify itself is
|
|
* really old, and likely has lines 16/17 mapped.
|
|
*/
|
|
lsdmr_common |= LSDMR_BSMA1617;
|
|
}
|
|
|
|
/*
|
|
* Issue PRECHARGE ALL command.
|
|
*/
|
|
lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
|
|
asm("sync;msync");
|
|
*sdram_addr = 0xff;
|
|
ppcDcbf((unsigned long) sdram_addr);
|
|
udelay(100);
|
|
|
|
/*
|
|
* Issue 8 AUTO REFRESH commands.
|
|
*/
|
|
for (idx = 0; idx < 8; idx++) {
|
|
lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
|
|
asm("sync;msync");
|
|
*sdram_addr = 0xff;
|
|
ppcDcbf((unsigned long) sdram_addr);
|
|
udelay(100);
|
|
}
|
|
|
|
/*
|
|
* Issue 8 MODE-set command.
|
|
*/
|
|
lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
|
|
asm("sync;msync");
|
|
*sdram_addr = 0xff;
|
|
ppcDcbf((unsigned long) sdram_addr);
|
|
udelay(100);
|
|
|
|
/*
|
|
* Issue NORMAL OP command.
|
|
*/
|
|
lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
|
|
asm("sync;msync");
|
|
*sdram_addr = 0xff;
|
|
ppcDcbf((unsigned long) sdram_addr);
|
|
udelay(200); /* Overkill. Must wait > 200 bus cycles */
|
|
|
|
#endif /* enable SDRAM init */
|
|
}
|
|
|
|
#ifdef CONFIG_PCI
|
|
/* For some reason the Tundra PCI bridge shows up on itself as a
|
|
* different device. Work around that by refusing to configure it
|
|
*/
|
|
void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
|
|
|
|
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
|
|
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
|
|
{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
|
|
{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
|
|
mpc85xx_config_via_usbide, {0,0,0}},
|
|
{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
|
|
mpc85xx_config_via_usb, {0,0,0}},
|
|
{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
|
|
mpc85xx_config_via_usb2, {0,0,0}},
|
|
{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
|
|
mpc85xx_config_via_power, {0,0,0}},
|
|
{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
|
|
mpc85xx_config_via_ac97, {0,0,0}},
|
|
{},
|
|
};
|
|
|
|
|
|
static struct pci_controller hose[] = {
|
|
{
|
|
config_table: pci_mpc85xxcds_config_table,
|
|
},
|
|
#ifdef CONFIG_MPC85XX_PCI2
|
|
{},
|
|
#endif
|
|
};
|
|
|
|
#endif
|
|
|
|
void
|
|
pci_init_board(void)
|
|
{
|
|
#ifdef CONFIG_PCI
|
|
pci_mpc85xx_init(hose);
|
|
#endif
|
|
}
|
|
|
|
#if defined(CONFIG_OF_BOARD_SETUP)
|
|
void
|
|
ft_pci_setup(void *blob, bd_t *bd)
|
|
{
|
|
int node, tmp[2];
|
|
const char *path;
|
|
|
|
node = fdt_path_offset(blob, "/aliases");
|
|
tmp[0] = 0;
|
|
if (node >= 0) {
|
|
#ifdef CONFIG_PCI1
|
|
path = fdt_getprop(blob, node, "pci0", NULL);
|
|
if (path) {
|
|
tmp[1] = hose[0].last_busno - hose[0].first_busno;
|
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
|
}
|
|
#endif
|
|
#ifdef CONFIG_MPC85XX_PCI2
|
|
path = fdt_getprop(blob, node, "pci1", NULL);
|
|
if (path) {
|
|
tmp[1] = hose[1].last_busno - hose[1].first_busno;
|
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
|
}
|
|
#endif
|
|
}
|
|
}
|
|
#endif
|