mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 05:06:16 +09:00
65dd74a674
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org>
80 lines
1.4 KiB
C
80 lines
1.4 KiB
C
/*
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* Copyright (c) 2014 Google, Inc
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*
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* From Coreboot src/lib/ramtest.c
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/post.h>
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static void write_phys(unsigned long addr, u32 value)
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{
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#if CONFIG_SSE2
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asm volatile(
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"movnti %1, (%0)"
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: /* outputs */
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: "r" (addr), "r" (value) /* inputs */
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: /* clobbers */
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);
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#else
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writel(value, addr);
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#endif
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}
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static u32 read_phys(unsigned long addr)
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{
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return readl(addr);
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}
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static void phys_memory_barrier(void)
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{
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#if CONFIG_SSE2
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/* Needed for movnti */
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asm volatile(
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"sfence"
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:
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:
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: "memory"
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);
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#else
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asm volatile(""
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:
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:
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: "memory");
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#endif
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}
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void quick_ram_check(void)
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{
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int fail = 0;
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u32 backup;
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backup = read_phys(CONFIG_RAMBASE);
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write_phys(CONFIG_RAMBASE, 0x55555555);
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phys_memory_barrier();
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if (read_phys(CONFIG_RAMBASE) != 0x55555555)
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fail = 1;
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write_phys(CONFIG_RAMBASE, 0xaaaaaaaa);
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phys_memory_barrier();
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if (read_phys(CONFIG_RAMBASE) != 0xaaaaaaaa)
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fail = 1;
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write_phys(CONFIG_RAMBASE, 0x00000000);
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phys_memory_barrier();
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if (read_phys(CONFIG_RAMBASE) != 0x00000000)
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fail = 1;
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write_phys(CONFIG_RAMBASE, 0xffffffff);
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phys_memory_barrier();
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if (read_phys(CONFIG_RAMBASE) != 0xffffffff)
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fail = 1;
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write_phys(CONFIG_RAMBASE, backup);
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if (fail) {
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post_code(POST_RAM_FAILURE);
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panic("RAM INIT FAILURE!\n");
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}
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phys_memory_barrier();
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}
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