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https://github.com/brain-hackers/u-boot-brain
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e6e505b93c
Some of the code in arch/arm/cpu/armv7/sunxi is actually armv7 specific, while most of it is just generic code that could as well be used on an AArch64 SoC. Move all files that are not really tied to armv7 into a new mach-sunxi directory. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
66 lines
1.4 KiB
C
66 lines
1.4 KiB
C
/*
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* (C) Copyright 2007-2012
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/prcm.h>
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#include <asm/arch/sys_proto.h>
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__weak void clock_init_sec(void)
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{
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}
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int clock_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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clock_init_safe();
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#endif
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clock_init_uart();
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clock_init_sec();
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return 0;
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}
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/* These functions are shared between various SoCs so put them here. */
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#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I
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int clock_twi_onoff(int port, int state)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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if (port == 5) {
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if (state)
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prcm_apb0_enable(
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PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
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else
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prcm_apb0_disable(
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PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
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return 0;
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}
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/* set the apb clock gate and reset for twi */
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if (state) {
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setbits_le32(&ccm->apb2_gate,
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CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port));
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setbits_le32(&ccm->apb2_reset_cfg,
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1 << (APB2_RESET_TWI_SHIFT + port));
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} else {
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clrbits_le32(&ccm->apb2_reset_cfg,
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1 << (APB2_RESET_TWI_SHIFT + port));
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clrbits_le32(&ccm->apb2_gate,
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CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port));
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}
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return 0;
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}
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#endif
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