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![Weijie Gao](/assets/img/avatar_default.png)
This patch adds spi-mem driver for MediaTek MT7629 SoC to access SPI-NOR and SPI-NAND flashes. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> [jagan: squash MAINTAINERS file] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
319 lines
7.0 KiB
C
319 lines
7.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 MediaTek Inc. All Rights Reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <spi.h>
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#include <spi-mem.h>
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#include <stdbool.h>
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#include <watchdog.h>
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#include <dm/pinctrl.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#define SNFI_MAC_CTL 0x500
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#define MAC_XIO_SEL BIT(4)
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#define SF_MAC_EN BIT(3)
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#define SF_TRIG BIT(2)
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#define WIP_READY BIT(1)
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#define WIP BIT(0)
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#define SNFI_MAC_OUTL 0x504
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#define SNFI_MAC_INL 0x508
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#define SNFI_MISC_CTL 0x538
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#define SW_RST BIT(28)
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#define FIFO_RD_LTC_SHIFT 25
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#define FIFO_RD_LTC GENMASK(26, 25)
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#define LATCH_LAT_SHIFT 8
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#define LATCH_LAT GENMASK(9, 8)
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#define CS_DESELECT_CYC_SHIFT 0
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#define CS_DESELECT_CYC GENMASK(4, 0)
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#define SNF_STA_CTL1 0x550
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#define SPI_STATE GENMASK(3, 0)
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#define SNFI_GPRAM_OFFSET 0x800
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#define SNFI_GPRAM_SIZE 0x80
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#define SNFI_POLL_INTERVAL 500000
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#define SNFI_RST_POLL_INTERVAL 1000000
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struct mtk_snfi_priv {
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void __iomem *base;
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struct clk nfi_clk;
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struct clk pad_clk;
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};
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static int mtk_snfi_adjust_op_size(struct spi_slave *slave,
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struct spi_mem_op *op)
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{
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u32 nbytes;
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/*
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* When there is input data, it will be appended after the output
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* data in the GPRAM. So the total size of either pure output data
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* or the output+input data must not exceed the GPRAM size.
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*/
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nbytes = sizeof(op->cmd.opcode) + op->addr.nbytes +
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op->dummy.nbytes;
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if (nbytes + op->data.nbytes <= SNFI_GPRAM_SIZE)
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return 0;
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if (nbytes >= SNFI_GPRAM_SIZE)
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return -ENOTSUPP;
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op->data.nbytes = SNFI_GPRAM_SIZE - nbytes;
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return 0;
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}
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static bool mtk_snfi_supports_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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if (op->cmd.buswidth > 1 || op->addr.buswidth > 1 ||
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op->dummy.buswidth > 1 || op->data.buswidth > 1)
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return false;
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return true;
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}
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static int mtk_snfi_mac_trigger(struct mtk_snfi_priv *priv,
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struct udevice *bus, u32 outlen, u32 inlen)
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{
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int ret;
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u32 val;
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#ifdef CONFIG_PINCTRL
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pinctrl_select_state(bus, "snfi");
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#endif
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writel(SF_MAC_EN, priv->base + SNFI_MAC_CTL);
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writel(outlen, priv->base + SNFI_MAC_OUTL);
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writel(inlen, priv->base + SNFI_MAC_INL);
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writel(SF_MAC_EN | SF_TRIG, priv->base + SNFI_MAC_CTL);
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ret = readl_poll_timeout(priv->base + SNFI_MAC_CTL, val,
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val & WIP_READY, SNFI_POLL_INTERVAL);
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if (ret) {
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printf("%s: timed out waiting for WIP_READY\n", __func__);
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goto cleanup;
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}
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ret = readl_poll_timeout(priv->base + SNFI_MAC_CTL, val,
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!(val & WIP), SNFI_POLL_INTERVAL);
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if (ret)
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printf("%s: timed out waiting for WIP cleared\n", __func__);
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writel(0, priv->base + SNFI_MAC_CTL);
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cleanup:
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#ifdef CONFIG_PINCTRL
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pinctrl_select_state(bus, "default");
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#endif
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return ret;
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}
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static int mtk_snfi_mac_reset(struct mtk_snfi_priv *priv)
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{
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int ret;
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u32 val;
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setbits_32(priv->base + SNFI_MISC_CTL, SW_RST);
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ret = readl_poll_timeout(priv->base + SNF_STA_CTL1, val,
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!(val & SPI_STATE), SNFI_POLL_INTERVAL);
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if (ret)
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printf("%s: failed to reset snfi mac\n", __func__);
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writel((2 << FIFO_RD_LTC_SHIFT) |
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(10 << CS_DESELECT_CYC_SHIFT),
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priv->base + SNFI_MISC_CTL);
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return ret;
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}
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static void mtk_snfi_copy_to_gpram(struct mtk_snfi_priv *priv,
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const void *data, size_t len)
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{
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void __iomem *gpram = priv->base + SNFI_GPRAM_OFFSET;
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size_t i, n = (len + sizeof(u32) - 1) / sizeof(u32);
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const u32 *buff = data;
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/*
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* The output data will always be copied to the beginning of
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* the GPRAM. Uses word write for better performace.
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*
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* Trailing bytes in the last word are not cared.
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*/
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for (i = 0; i < n; i++)
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writel(buff[i], gpram + i * sizeof(u32));
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}
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static void mtk_snfi_copy_from_gpram(struct mtk_snfi_priv *priv, u8 *cache,
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void *data, size_t pos, size_t len)
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{
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void __iomem *gpram = priv->base + SNFI_GPRAM_OFFSET;
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u32 *buff = (u32 *)cache;
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size_t i, off, end;
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/* Start position in the buffer */
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off = pos & (sizeof(u32) - 1);
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/* End position for copy */
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end = (len + pos + sizeof(u32) - 1) & (~(sizeof(u32) - 1));
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/* Start position for copy */
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pos &= ~(sizeof(u32) - 1);
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/*
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* Read aligned data from GPRAM to buffer first.
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* Uses word read for better performace.
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*/
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i = 0;
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while (pos < end) {
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buff[i++] = readl(gpram + pos);
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pos += sizeof(u32);
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}
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/* Copy rx data */
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memcpy(data, cache + off, len);
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}
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static int mtk_snfi_exec_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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struct udevice *bus = dev_get_parent(slave->dev);
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struct mtk_snfi_priv *priv = dev_get_priv(bus);
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u8 gpram_cache[SNFI_GPRAM_SIZE];
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u32 i, len = 0, inlen = 0;
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int addr_sh;
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int ret;
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WATCHDOG_RESET();
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ret = mtk_snfi_mac_reset(priv);
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if (ret)
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return ret;
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/* Put opcode */
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gpram_cache[len++] = op->cmd.opcode;
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/* Put address */
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addr_sh = (op->addr.nbytes - 1) * 8;
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while (addr_sh >= 0) {
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gpram_cache[len++] = (op->addr.val >> addr_sh) & 0xff;
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addr_sh -= 8;
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}
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/* Put dummy bytes */
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for (i = 0; i < op->dummy.nbytes; i++)
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gpram_cache[len++] = 0;
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/* Put output data */
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if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) {
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memcpy(gpram_cache + len, op->data.buf.out, op->data.nbytes);
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len += op->data.nbytes;
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}
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/* Copy final output data to GPRAM */
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mtk_snfi_copy_to_gpram(priv, gpram_cache, len);
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/* Start one SPI transaction */
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if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
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inlen = op->data.nbytes;
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ret = mtk_snfi_mac_trigger(priv, bus, len, inlen);
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if (ret)
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return ret;
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/* Copy input data from GPRAM */
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if (inlen)
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mtk_snfi_copy_from_gpram(priv, gpram_cache, op->data.buf.in,
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len, inlen);
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return 0;
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}
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static int mtk_snfi_spi_probe(struct udevice *bus)
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{
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struct mtk_snfi_priv *priv = dev_get_priv(bus);
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int ret;
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priv->base = (void __iomem *)devfdt_get_addr(bus);
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if (!priv->base)
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return -EINVAL;
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ret = clk_get_by_name(bus, "nfi_clk", &priv->nfi_clk);
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if (ret < 0)
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return ret;
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ret = clk_get_by_name(bus, "pad_clk", &priv->pad_clk);
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if (ret < 0)
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return ret;
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clk_enable(&priv->nfi_clk);
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clk_enable(&priv->pad_clk);
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return 0;
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}
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static int mtk_snfi_set_speed(struct udevice *bus, uint speed)
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{
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/*
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* The SNFI does not have a bus clock divider.
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* The bus clock is set in dts (pad_clk, UNIVPLL2_D8 = 50MHz).
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*/
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return 0;
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}
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static int mtk_snfi_set_mode(struct udevice *bus, uint mode)
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{
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/* The SNFI supports only mode 0 */
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if (mode)
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return -EINVAL;
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return 0;
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}
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static const struct spi_controller_mem_ops mtk_snfi_mem_ops = {
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.adjust_op_size = mtk_snfi_adjust_op_size,
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.supports_op = mtk_snfi_supports_op,
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.exec_op = mtk_snfi_exec_op,
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};
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static const struct dm_spi_ops mtk_snfi_spi_ops = {
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.mem_ops = &mtk_snfi_mem_ops,
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.set_speed = mtk_snfi_set_speed,
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.set_mode = mtk_snfi_set_mode,
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};
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static const struct udevice_id mtk_snfi_spi_ids[] = {
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{ .compatible = "mediatek,mtk-snfi-spi" },
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{ }
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};
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U_BOOT_DRIVER(mtk_snfi_spi) = {
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.name = "mtk_snfi_spi",
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.id = UCLASS_SPI,
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.of_match = mtk_snfi_spi_ids,
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.ops = &mtk_snfi_spi_ops,
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.priv_auto_alloc_size = sizeof(struct mtk_snfi_priv),
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.probe = mtk_snfi_spi_probe,
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};
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