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![Peng Fan](/assets/img/avatar_default.png)
Since we added clk enable_count and prograte clk child enabling operation to clk parent, so add a new function sandbox_clk_enable_count to get enable_count for test usage. And add test code to get the enable_count after we enable/disable the device clk. Signed-off-by: Peng Fan <peng.fan@nxp.com>
281 lines
6.2 KiB
C
281 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*
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* Common Clock Framework [CCF] driver for Sandbox
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*/
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#include <common.h>
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#include <dm.h>
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#include <clk.h>
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#include <asm/clk.h>
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#include <clk-uclass.h>
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#include <linux/clk-provider.h>
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#include <sandbox-clk.h>
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/*
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* Sandbox implementation of CCF primitives necessary for clk-uclass testing
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*
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* --- Sandbox PLLv3 ---
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*/
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struct clk_pllv3 {
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struct clk clk;
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u32 div_mask;
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u32 div_shift;
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};
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int sandbox_clk_enable_count(struct clk *clk)
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{
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struct clk *clkp = NULL;
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int ret;
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ret = clk_get_by_id(clk->id, &clkp);
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if (ret)
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return 0;
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return clkp->enable_count;
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}
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static ulong clk_pllv3_get_rate(struct clk *clk)
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{
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unsigned long parent_rate = clk_get_parent_rate(clk);
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return parent_rate * 24;
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}
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static const struct clk_ops clk_pllv3_generic_ops = {
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.get_rate = clk_pllv3_get_rate,
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};
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struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
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const char *parent_name, void __iomem *base,
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u32 div_mask)
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{
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struct clk_pllv3 *pll;
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struct clk *clk;
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char *drv_name = "sandbox_clk_pllv3";
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int ret;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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pll->div_mask = div_mask;
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clk = &pll->clk;
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ret = clk_register(clk, drv_name, name, parent_name);
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if (ret) {
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kfree(pll);
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return ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(sandbox_clk_pll_generic) = {
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.name = "sandbox_clk_pllv3",
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.id = UCLASS_CLK,
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.ops = &clk_pllv3_generic_ops,
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};
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/* --- Sandbox PLLv3 --- */
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/* --- Sandbox Gate --- */
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struct clk_gate2 {
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struct clk clk;
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bool state;
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};
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#define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
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static int clk_gate2_enable(struct clk *clk)
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{
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struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
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gate->state = 1;
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return 0;
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}
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static int clk_gate2_disable(struct clk *clk)
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{
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struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
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gate->state = 0;
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return 0;
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}
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static const struct clk_ops clk_gate2_ops = {
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.enable = clk_gate2_enable,
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.disable = clk_gate2_disable,
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.get_rate = clk_generic_get_rate,
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};
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struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
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const char *parent_name,
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unsigned long flags, void __iomem *reg,
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u8 bit_idx, u8 cgr_val,
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u8 clk_gate2_flags)
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{
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struct clk_gate2 *gate;
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struct clk *clk;
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int ret;
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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gate->state = 0;
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clk = &gate->clk;
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ret = clk_register(clk, "sandbox_clk_gate2", name, parent_name);
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if (ret) {
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kfree(gate);
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return ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(sandbox_clk_gate2) = {
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.name = "sandbox_clk_gate2",
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.id = UCLASS_CLK,
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.ops = &clk_gate2_ops,
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};
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static unsigned long sandbox_clk_composite_divider_recalc_rate(struct clk *clk)
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{
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struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
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struct clk_composite *composite = (struct clk_composite *)clk->data;
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ulong parent_rate = clk_get_parent_rate(&composite->clk);
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unsigned int val;
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val = divider->io_divider_val;
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val >>= divider->shift;
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val &= clk_div_mask(divider->width);
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return divider_recalc_rate(clk, parent_rate, val, divider->table,
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divider->flags, divider->width);
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}
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static const struct clk_ops sandbox_clk_composite_divider_ops = {
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.get_rate = sandbox_clk_composite_divider_recalc_rate,
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};
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struct clk *sandbox_clk_composite(const char *name,
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const char * const *parent_names,
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int num_parents, void __iomem *reg,
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unsigned long flags)
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{
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struct clk *clk = ERR_PTR(-ENOMEM);
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struct clk_divider *div = NULL;
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struct clk_gate *gate = NULL;
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struct clk_mux *mux = NULL;
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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goto fail;
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mux->reg = reg;
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mux->shift = 24;
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mux->mask = 0x7;
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mux->num_parents = num_parents;
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mux->flags = flags;
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mux->parent_names = parent_names;
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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goto fail;
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div->reg = reg;
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div->shift = 16;
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div->width = 3;
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div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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goto fail;
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gate->reg = reg;
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gate->bit_idx = 28;
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gate->flags = flags;
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clk = clk_register_composite(NULL, name,
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parent_names, num_parents,
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&mux->clk, &clk_mux_ops, &div->clk,
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&sandbox_clk_composite_divider_ops,
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&gate->clk, &clk_gate_ops, flags);
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if (IS_ERR(clk))
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goto fail;
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return clk;
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fail:
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kfree(gate);
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kfree(div);
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kfree(mux);
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return ERR_CAST(clk);
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}
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/* --- Sandbox Gate --- */
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/* The CCF core driver itself */
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static const struct udevice_id sandbox_clk_ccf_test_ids[] = {
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{ .compatible = "sandbox,clk-ccf" },
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{ }
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};
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static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", };
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static const char *const i2c_sels[] = { "pll3_60m", "pll3_80m", };
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static int sandbox_clk_ccf_probe(struct udevice *dev)
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{
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void *base = NULL;
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u32 reg;
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clk_dm(SANDBOX_CLK_PLL3,
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sandbox_clk_pllv3(SANDBOX_PLLV3_USB, "pll3_usb_otg", "osc",
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base + 0x10, 0x3));
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clk_dm(SANDBOX_CLK_PLL3_60M,
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sandbox_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
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clk_dm(SANDBOX_CLK_PLL3_80M,
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sandbox_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
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/* The HW adds +1 to the divider value (2+1) is the divider */
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reg = (2 << 19);
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clk_dm(SANDBOX_CLK_ECSPI_ROOT,
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sandbox_clk_divider("ecspi_root", "pll3_60m", ®, 19, 6));
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clk_dm(SANDBOX_CLK_ECSPI1,
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sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
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/* Select 'pll3_60m' */
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reg = 0;
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clk_dm(SANDBOX_CLK_USDHC1_SEL,
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sandbox_clk_mux("usdhc1_sel", ®, 16, 1, usdhc_sels,
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ARRAY_SIZE(usdhc_sels)));
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/* Select 'pll3_80m' */
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reg = BIT(17);
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clk_dm(SANDBOX_CLK_USDHC2_SEL,
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sandbox_clk_mux("usdhc2_sel", ®, 17, 1, usdhc_sels,
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ARRAY_SIZE(usdhc_sels)));
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reg = BIT(28) | BIT(24) | BIT(16);
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clk_dm(SANDBOX_CLK_I2C,
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sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels),
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®, 0));
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clk_dm(SANDBOX_CLK_I2C_ROOT,
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sandbox_clk_gate2("i2c_root", "i2c", base + 0x7c, 0));
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return 0;
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}
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U_BOOT_DRIVER(sandbox_clk_ccf) = {
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.name = "sandbox_clk_ccf",
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.id = UCLASS_CLK,
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.probe = sandbox_clk_ccf_probe,
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.of_match = sandbox_clk_ccf_test_ids,
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};
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