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![Mario Six](/assets/img/avatar_default.png)
The ihs_video_out driver's error handling is incorrect in two places (one is a missing negation, and in one place a error should be ignored). Fix these two instances. Signed-off-by: Mario Six <mario.six@gdsys.cc>
342 lines
8.4 KiB
C
342 lines
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2017
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* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
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*
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* based on the gdsys osd driver, which is
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*
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* (C) Copyright 2010
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.de
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*/
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#include <common.h>
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#include <display.h>
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#include <dm.h>
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#include <regmap.h>
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#include <video_osd.h>
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#include <asm/gpio.h>
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static const uint MAX_X_CHARS = 53;
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static const uint MAX_Y_CHARS = 26;
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static const uint MAX_VIDEOMEM_WIDTH = 64;
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static const uint MAX_VIDEOMEM_HEIGHT = 32;
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static const uint CHAR_WIDTH = 12;
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static const uint CHAR_HEIGHT = 18;
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static const u16 BASE_WIDTH_MASK = 0x3f00;
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static const uint BASE_WIDTH_SHIFT = 8;
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static const u16 BASE_HEIGTH_MASK = 0x001f;
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static const uint BASE_HEIGTH_SHIFT;
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struct ihs_video_out_regs {
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/* Device version register */
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u16 versions;
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/* Device feature register */
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u16 features;
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/* Device control register */
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u16 control;
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/* Register controlling screen size */
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u16 xy_size;
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/* Register controlling screen scaling */
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u16 xy_scale;
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/* Register controlling screen x position */
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u16 x_pos;
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/* Register controlling screen y position */
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u16 y_pos;
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};
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#define ihs_video_out_set(map, member, val) \
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regmap_range_set(map, 1, struct ihs_video_out_regs, member, val)
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#define ihs_video_out_get(map, member, valp) \
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regmap_range_get(map, 1, struct ihs_video_out_regs, member, valp)
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enum {
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CONTROL_FILTER_BLACK = (0 << 0),
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CONTROL_FILTER_ORIGINAL = (1 << 0),
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CONTROL_FILTER_DARKER = (2 << 0),
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CONTROL_FILTER_GRAY = (3 << 0),
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CONTROL_MODE_PASSTHROUGH = (0 << 3),
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CONTROL_MODE_OSD = (1 << 3),
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CONTROL_MODE_AUTO = (2 << 3),
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CONTROL_MODE_OFF = (3 << 3),
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CONTROL_ENABLE_OFF = (0 << 6),
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CONTROL_ENABLE_ON = (1 << 6),
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};
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struct ihs_video_out_priv {
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/* Register map for OSD device */
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struct regmap *map;
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/* Pointer to video memory */
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u16 *vidmem;
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/* Display width in text columns */
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uint base_width;
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/* Display height in text rows */
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uint base_height;
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/* x-resolution of the display in pixels */
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uint res_x;
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/* y-resolution of the display in pixels */
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uint res_y;
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/* OSD's sync mode (resolution + frequency) */
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int sync_src;
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/* The display port output for this OSD */
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struct udevice *video_tx;
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/* The pixel clock generator for the display */
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struct udevice *clk_gen;
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};
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static const struct udevice_id ihs_video_out_ids[] = {
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{ .compatible = "gdsys,ihs_video_out" },
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{ }
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};
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/**
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* set_control() - Set the control register to a given value
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*
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* The current value of sync_src is preserved by the function automatically.
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*
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* @dev: the OSD device whose control register to set
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* @value: the 16-bit value to write to the control register
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* Return: 0
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*/
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static int set_control(struct udevice *dev, u16 value)
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{
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struct ihs_video_out_priv *priv = dev_get_priv(dev);
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if (priv->sync_src)
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value |= ((priv->sync_src & 0x7) << 8);
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ihs_video_out_set(priv->map, control, value);
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return 0;
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}
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int ihs_video_out_get_info(struct udevice *dev, struct video_osd_info *info)
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{
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struct ihs_video_out_priv *priv = dev_get_priv(dev);
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u16 versions;
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ihs_video_out_get(priv->map, versions, &versions);
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info->width = priv->base_width;
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info->height = priv->base_height;
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info->major_version = versions / 100;
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info->minor_version = versions % 100;
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return 0;
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}
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int ihs_video_out_set_mem(struct udevice *dev, uint col, uint row, u8 *buf,
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size_t buflen, uint count)
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{
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struct ihs_video_out_priv *priv = dev_get_priv(dev);
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int res;
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uint offset;
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uint k, rep;
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u16 data;
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/* Repetitions (controlled via count parmeter) */
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for (rep = 0; rep < count; ++rep) {
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offset = row * priv->base_width + col + rep * (buflen / 2);
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/* Write a single buffer copy */
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for (k = 0; k < buflen / 2; ++k) {
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uint max_size = priv->base_width * priv->base_height;
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if (offset + k >= max_size) {
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debug("%s: Write would be out of OSD bounds\n",
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dev->name);
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return -E2BIG;
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}
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data = buf[2 * k + 1] + 256 * buf[2 * k];
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out_le16(priv->vidmem + offset + k, data);
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}
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}
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res = set_control(dev, CONTROL_FILTER_ORIGINAL |
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CONTROL_MODE_OSD |
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CONTROL_ENABLE_ON);
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if (res) {
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debug("%s: Could not set control register\n", dev->name);
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return res;
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}
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return 0;
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}
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/**
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* div2_u16() - Approximately divide a 16-bit number by 2
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*
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* @val: The 16-bit value to divide by two
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* Return: The approximate division of val by two
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*/
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static inline u16 div2_u16(u16 val)
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{
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return (32767 * val) / 65535;
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}
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int ihs_video_out_set_size(struct udevice *dev, uint col, uint row)
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{
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struct ihs_video_out_priv *priv = dev_get_priv(dev);
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if (!col || col > MAX_VIDEOMEM_WIDTH || col > MAX_X_CHARS ||
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!row || row > MAX_VIDEOMEM_HEIGHT || row > MAX_Y_CHARS) {
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debug("%s: Desired OSD size invalid\n", dev->name);
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return -EINVAL;
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}
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ihs_video_out_set(priv->map, xy_size, ((col - 1) << 8) | (row - 1));
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/* Center OSD on screen */
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ihs_video_out_set(priv->map, x_pos,
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div2_u16(priv->res_x - CHAR_WIDTH * col));
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ihs_video_out_set(priv->map, y_pos,
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div2_u16(priv->res_y - CHAR_HEIGHT * row));
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return 0;
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}
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int ihs_video_out_print(struct udevice *dev, uint col, uint row, ulong color,
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char *text)
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{
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int res;
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u8 buffer[2 * MAX_VIDEOMEM_WIDTH];
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uint k;
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uint charcount = strlen(text);
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uint len = min(charcount, 2 * MAX_VIDEOMEM_WIDTH);
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for (k = 0; k < len; ++k) {
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buffer[2 * k] = text[k];
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buffer[2 * k + 1] = color;
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}
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res = ihs_video_out_set_mem(dev, col, row, buffer, 2 * len, 1);
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if (res < 0) {
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debug("%s: Could not write to video memory\n", dev->name);
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return res;
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}
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return 0;
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}
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static const struct video_osd_ops ihs_video_out_ops = {
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.get_info = ihs_video_out_get_info,
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.set_mem = ihs_video_out_set_mem,
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.set_size = ihs_video_out_set_size,
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.print = ihs_video_out_print,
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};
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int ihs_video_out_probe(struct udevice *dev)
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{
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struct ihs_video_out_priv *priv = dev_get_priv(dev);
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struct ofnode_phandle_args phandle_args;
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const char *mode;
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u16 features;
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struct display_timing timing;
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int res;
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res = regmap_init_mem(dev_ofnode(dev), &priv->map);
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if (res) {
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debug("%s: Could not initialize regmap (err = %d)\n", dev->name,
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res);
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return res;
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}
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/* Range with index 2 is video memory */
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priv->vidmem = regmap_get_range(priv->map, 2);
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mode = dev_read_string(dev, "mode");
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if (!mode) {
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debug("%s: Could not read mode property\n", dev->name);
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return -EINVAL;
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}
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if (!strcmp(mode, "1024_768_60")) {
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priv->sync_src = 2;
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priv->res_x = 1024;
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priv->res_y = 768;
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timing.hactive.typ = 1024;
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timing.vactive.typ = 768;
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} else if (!strcmp(mode, "720_400_70")) {
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priv->sync_src = 1;
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priv->res_x = 720;
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priv->res_y = 400;
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timing.hactive.typ = 720;
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timing.vactive.typ = 400;
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} else {
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priv->sync_src = 0;
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priv->res_x = 640;
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priv->res_y = 480;
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timing.hactive.typ = 640;
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timing.vactive.typ = 480;
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}
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ihs_video_out_get(priv->map, features, &features);
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res = set_control(dev, CONTROL_FILTER_ORIGINAL |
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CONTROL_MODE_OSD |
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CONTROL_ENABLE_OFF);
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if (res) {
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debug("%s: Could not set control register (err = %d)\n",
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dev->name, res);
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return res;
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}
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priv->base_width = ((features & BASE_WIDTH_MASK)
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>> BASE_WIDTH_SHIFT) + 1;
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priv->base_height = ((features & BASE_HEIGTH_MASK)
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>> BASE_HEIGTH_SHIFT) + 1;
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res = dev_read_phandle_with_args(dev, "clk_gen", NULL, 0, 0,
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&phandle_args);
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if (res) {
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debug("%s: Could not get clk_gen node (err = %d)\n",
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dev->name, res);
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return -EINVAL;
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}
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res = uclass_get_device_by_ofnode(UCLASS_CLK, phandle_args.node,
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&priv->clk_gen);
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if (res) {
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debug("%s: Could not get clk_gen dev (err = %d)\n",
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dev->name, res);
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return -EINVAL;
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}
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res = dev_read_phandle_with_args(dev, "video_tx", NULL, 0, 0,
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&phandle_args);
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if (res) {
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debug("%s: Could not get video_tx (err = %d)\n",
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dev->name, res);
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return -EINVAL;
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}
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res = uclass_get_device_by_ofnode(UCLASS_DISPLAY, phandle_args.node,
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&priv->video_tx);
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if (res) {
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debug("%s: Could not get video_tx dev (err = %d)\n",
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dev->name, res);
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return -EINVAL;
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}
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res = display_enable(priv->video_tx, 8, &timing);
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if (res && res != -EIO) { /* Ignore missing DP sink error */
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debug("%s: Could not enable the display (err = %d)\n",
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dev->name, res);
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return res;
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}
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return 0;
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}
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U_BOOT_DRIVER(ihs_video_out_drv) = {
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.name = "ihs_video_out_drv",
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.id = UCLASS_VIDEO_OSD,
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.ops = &ihs_video_out_ops,
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.of_match = ihs_video_out_ids,
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.probe = ihs_video_out_probe,
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.priv_auto_alloc_size = sizeof(struct ihs_video_out_priv),
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};
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