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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
173 lines
4.6 KiB
C
173 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/flow.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/pmc.h>
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#include <asm/arch-tegra/tegra_i2c.h>
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#include "../cpu.h"
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/* Tegra30-specific CPU init code */
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void tegra_i2c_ll_write_addr(uint addr, uint config)
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{
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struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
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writel(addr, ®->cmd_addr0);
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writel(config, ®->cnfg);
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}
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void tegra_i2c_ll_write_data(uint data, uint config)
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{
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struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
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writel(data, ®->cmd_data1);
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writel(config, ®->cnfg);
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}
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#define TPS62366A_I2C_ADDR 0xC0
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#define TPS62366A_SET1_REG 0x01
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#define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG)
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#define TPS62361B_I2C_ADDR 0xC0
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#define TPS62361B_SET3_REG 0x03
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#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG)
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#define TPS65911_I2C_ADDR 0x5A
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#define TPS65911_VDDCTRL_OP_REG 0x28
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#define TPS65911_VDDCTRL_SR_REG 0x27
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#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
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#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
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#define I2C_SEND_2_BYTES 0x0A02
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static void enable_cpu_power_rail(void)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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u32 reg;
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debug("enable_cpu_power_rail entry\n");
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reg = readl(&pmc->pmc_cntrl);
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reg |= CPUPWRREQ_OE;
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writel(reg, &pmc->pmc_cntrl);
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/* Set VDD_CORE to 1.200V. */
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#ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
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tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR, 2);
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tegra_i2c_ll_write_data(TPS62366A_SET1_DATA, I2C_SEND_2_BYTES);
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#endif
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#ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
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tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR, 2);
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tegra_i2c_ll_write_data(TPS62361B_SET3_DATA, I2C_SEND_2_BYTES);
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#endif
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udelay(1000);
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/*
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* Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
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* First set VDD to 1.0125V, then enable the VDD regulator.
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*/
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tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
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tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
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udelay(1000);
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tegra_i2c_ll_write_data(TPS65911_VDDCTRL_SR_DATA, I2C_SEND_2_BYTES);
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udelay(10 * 1000);
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}
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/**
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* The T30 requires some special clock initialization, including setting up
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* the dvc i2c, turning on mselect and selecting the G CPU cluster
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*/
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void t30_init_clocks(void)
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{
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
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u32 val;
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debug("t30_init_clocks entry\n");
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/* Set active CPU cluster to G */
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clrbits_le32(flow->cluster_control, 1 << 0);
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writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
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val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
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(1 << CLK_SYS_RATE_AHB_RATE_SHIFT) |
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(0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) |
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(0 << CLK_SYS_RATE_APB_RATE_SHIFT);
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writel(val, &clkrst->crc_clk_sys_rate);
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/* Put i2c, mselect in reset and enable clocks */
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reset_set_enable(PERIPH_ID_DVC_I2C, 1);
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clock_set_enable(PERIPH_ID_DVC_I2C, 1);
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reset_set_enable(PERIPH_ID_MSELECT, 1);
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clock_set_enable(PERIPH_ID_MSELECT, 1);
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/* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */
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clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2);
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/*
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* Our high-level clock routines are not available prior to
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* relocation. We use the low-level functions which require a
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* hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)
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*/
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clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16);
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/*
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* Give clocks time to stabilize, then take i2c and mselect out of
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* reset
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*/
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udelay(1000);
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reset_set_enable(PERIPH_ID_DVC_I2C, 0);
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reset_set_enable(PERIPH_ID_MSELECT, 0);
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}
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static void set_cpu_running(int run)
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{
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struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
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debug("set_cpu_running entry, run = %d\n", run);
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writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events);
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}
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void start_cpu(u32 reset_vector)
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{
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debug("start_cpu entry, reset_vector = %x\n", reset_vector);
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t30_init_clocks();
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/* Enable VDD_CPU */
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enable_cpu_power_rail();
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set_cpu_running(0);
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/* Hold the CPUs in reset */
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reset_A9_cpu(1);
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/* Disable the CPU clock */
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enable_cpu_clock(0);
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/* Enable CoreSight */
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clock_enable_coresight(1);
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/*
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* Set the entry point for CPU execution from reset,
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* if it's a non-zero value.
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*/
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if (reset_vector)
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writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
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/* Enable the CPU clock */
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enable_cpu_clock(1);
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/* If the CPU doesn't already have power, power it up */
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powerup_cpu();
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/* Take the CPU out of reset */
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reset_A9_cpu(0);
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set_cpu_running(1);
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}
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