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https://github.com/brain-hackers/u-boot-brain
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199537309b
Add support for DH Electronics DHCOM SoM and PDK2 rev. 400 carrier board. This is an SoM with STM32MP15xx and an evaluation kit. The baseboard provides Ethernet, UART, USB, CAN and optional display. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
89 lines
2.3 KiB
Plaintext
89 lines
2.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2019 Marek Vasut <marex@denx.de>
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*/
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#include "stm32mp15xx-dhcom.dtsi"
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/ {
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model = "STMicroelectronics STM32MP15xx DHCOM Premium Developer Kit (2)";
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compatible = "dh,stm32mp15xx-dhcom-pdk2", "st,stm32mp15x";
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aliases {
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serial0 = &uart4;
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ethernet0 = ðernet0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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ethernet_vio: vioregulator {
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compatible = "regulator-fixed";
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regulator-name = "vio";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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ðernet0 {
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status = "okay";
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pinctrl-0 = <ðernet0_rmii_pins_a>;
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pinctrl-1 = <ðernet0_rmii_pins_sleep_a>;
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pinctrl-names = "default", "sleep";
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phy-mode = "rmii";
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max-speed = <100>;
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phy-handle = <&phy0>;
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st,eth_ref_clk_sel;
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phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
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mdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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&pinctrl {
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ethernet0_rmii_pins_a: rmii-0 {
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pins1 {
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pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
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<STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
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<STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
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<STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
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<STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
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<STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
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<STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
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<STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
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bias-disable;
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};
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};
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ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
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pins1 {
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pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
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<STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
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<STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
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<STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
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<STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
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<STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
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<STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
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<STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
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<STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
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};
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};
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};
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