mirror of
https://github.com/brain-hackers/u-boot-brain
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46263f2de4
This commit adapts the files that were derived from PIBS (PowerPC Initialization and Boot Software) codeto using SPDX License Identifiers. So far, SPDX has not assigned an official License ID for the PIBS license yet, so this should be considered preliminary. Note that the following files contained incorrect license information: arch/powerpc/cpu/ppc4xx/4xx_uart.c arch/powerpc/cpu/ppc4xx/start.S arch/powerpc/include/asm/ppc440.h These files included, in addition to the GPL-2.0 / ibm-pibs dual license as inherited from PIBS, a GPL-2.0+ license header which was obviously incorrect. This has been removed. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Wolfgang Denk <wd@denx.de> Conflicts: Licenses/README Acked-by: Stefan Roese <sr@denx.de>
202 lines
6.0 KiB
ArmAsm
202 lines
6.0 KiB
ArmAsm
/*
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* SPDX-License-Identifier: GPL-2.0 ibm-pibs
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*/
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/*-----------------------------------------------------------------------------
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* Function: ext_bus_cntlr_init
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* Description: Initializes the External Bus Controller for the external
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* peripherals. IMPORTANT: For pass1 this code must run from
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* cache since you can not reliably change a peripheral banks
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* timing register (pbxap) while running code from that bank.
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* For ex., since we are running from ROM on bank 0, we can NOT
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* execute the code that modifies bank 0 timings from ROM, so
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* we run it from cache.
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* Bank 0 - Flash or Multi Purpose Socket
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* Bank 1 - Multi Purpose Socket or Flash (set in C-Code)
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* Bank 2 - UART 1 (set in C-Code)
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* Bank 3 - UART 2 (set in C-Code)
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* Bank 4 - not used
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* Bank 5 - not used
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* Bank 6 - not used
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* Bank 7 - PLD Register
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*-----------------------------------------------------------------------------*/
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
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#include <configs/MIP405.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <asm/ppc4xx.h>
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#include "mip405.h"
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.globl ext_bus_cntlr_init
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ext_bus_cntlr_init:
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mflr r4 /* save link register */
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mfdcr r3,CPC0_PSR /* get strapping reg */
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andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
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bnelr /* jump back if PCI boot */
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bl ..getAddr
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..getAddr:
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mflr r3 /* get address of ..getAddr */
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mtlr r4 /* restore link register */
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addi r4,0,14 /* set ctr to 14; used to prefetch */
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mtctr r4 /* 14 cache lines to fit this function */
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/* in cache (gives us 8x14=112 instrctns) */
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..ebcloop:
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icbt r0,r3 /* prefetch cache line for addr in r3 */
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addi r3,r3,32 /* move to next cache line */
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bdnz ..ebcloop /* continue for 14 cache lines */
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/*-------------------------------------------------------------------
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* Delay to ensure all accesses to ROM are complete before changing
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* bank 0 timings.
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*------------------------------------------------------------------- */
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addis r3,0,0x0
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ori r3,r3,0xA000
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mtctr r3
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..spinlp:
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bdnz ..spinlp /* spin loop */
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/*-----------------------------------------------------------------------
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* decide boot up mode
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*----------------------------------------------------------------------- */
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addi r4,0,PB0CR
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mtdcr EBC0_CFGADDR,r4
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mfdcr r4,EBC0_CFGDATA
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andi. r0, r4, 0x2000 /* mask out irrelevant bits */
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beq 0f /* jump if 8 bit bus width */
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/* setup 16 bit things
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*-----------------------------------------------------------------------
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* Memory Bank 0 (16 Bit Flash) initialization
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*---------------------------------------------------------------------- */
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addi r4,0,PB1AP
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,(FLASH_AP_B)@h
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ori r4,r4,(FLASH_AP_B)@l
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB0CR
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mtdcr EBC0_CFGADDR,r4
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/* BS=0x010(4MB),BU=0x3(R/W), */
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addis r4,0,(FLASH_CR_B)@h
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ori r4,r4,(FLASH_CR_B)@l
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mtdcr EBC0_CFGDATA,r4
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b 1f
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0:
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/* 8Bit boot mode: */
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/*-----------------------------------------------------------------------
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* Memory Bank 0 Multi Purpose Socket initialization
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*----------------------------------------------------------------------- */
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/* 0x7F8FFE80 slowest boot */
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addi r4,0,PB1AP
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,(MPS_AP_B)@h
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ori r4,r4,(MPS_AP_B)@l
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB0CR
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mtdcr EBC0_CFGADDR,r4
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/* BS=0x010(4MB),BU=0x3(R/W), */
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addis r4,0,(MPS_CR_B)@h
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ori r4,r4,(MPS_CR_B)@l
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mtdcr EBC0_CFGDATA,r4
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1:
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/*-----------------------------------------------------------------------
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* Memory Bank 2-3-4-5-6 (not used) initialization
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*-----------------------------------------------------------------------*/
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addi r4,0,PB1CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0x0000
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ori r4,r4,0x0000
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB2CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0x0000
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ori r4,r4,0x0000
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB3CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0x0000
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ori r4,r4,0x0000
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB4CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0x0000
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ori r4,r4,0x0000
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB5CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0x0000
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ori r4,r4,0x0000
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB6CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0x0000
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ori r4,r4,0x0000
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB7CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0x0000
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ori r4,r4,0x0000
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mtdcr EBC0_CFGDATA,r4
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nop /* pass2 DCR errata #8 */
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blr
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#if defined(CONFIG_BOOT_PCI)
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.section .bootpg,"ax"
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.globl _start_pci
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/*******************************************
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*/
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_start_pci:
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/* first handle errata #68 / PCI_18 */
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iccci r0, r0 /* invalidate I-cache */
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lis r31, 0
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mticcr r31 /* ICCR = 0 (all uncachable) */
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isync
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mfccr0 r28 /* set CCR0[24] = 1 */
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ori r28, r28, 0x0080
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mtccr0 r28
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/* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
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lis r28, 0xEF40
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addi r28, r28, 0x0004
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stw r31, 0x0C(r28) /* clear PMM0PCIHA */
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lis r29, 0xFFF8 /* open 512 kByte */
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addi r29, r29, 0x0001/* and enable this region */
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stwbrx r29, r0, r28 /* write PMM0MA */
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lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */
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addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */
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lis r31, 0x8000 /* set en bit bus 0 */
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ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
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stwbrx r31, r0, r28 /* write it */
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lwbrx r31, r0, r29 /* load XBCS register */
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oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
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stwbrx r31, r0, r29 /* write back XBCS register */
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nop
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nop
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b _start /* normal start */
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#endif
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