mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-08 12:16:16 +09:00
e5ffa4bb62
According to Atom E6xx datasheet, setting VGA Disable (bit17) of Graphics Controller register (offset 0x50) prevents IGD (D2:F0) from reporting itself as a VGA display controller class in the PCI configuration space, and should also prevent it from responding to VGA legacy memory range and I/O addresses. However test result shows that with just VGA Disable bit set and a PCIe graphics card connected to one of the PCIe controllers on the E6xx, accessing the VGA legacy space still causes system hang. After a number of attempts, it turns out besides VGA Disable bit, the SDVO (D3:F0) device should be disabled to make it work. To simplify, use the Function Disable register (offset 0xc4) to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these two devices will be completely disabled (invisible in the PCI configuration space) unless a system reset is performed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
||
|---|---|---|
| .. | ||
| baytrail | ||
| coreboot | ||
| efi | ||
| ivybridge | ||
| qemu | ||
| quark | ||
| queensbay | ||
| call32.S | ||
| call64.S | ||
| config.mk | ||
| cpu_x86.c | ||
| cpu.c | ||
| interrupts.c | ||
| ioapic.c | ||
| irq.c | ||
| lapic.c | ||
| Makefile | ||
| mp_init.c | ||
| mtrr.c | ||
| pci.c | ||
| resetvec.S | ||
| sipi_vector.S | ||
| start.S | ||
| start16.S | ||
| turbo.c | ||
| u-boot.lds | ||