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060f9bf57b
The cacheline is always 32 bytes for arm1176 CPUs, so define it at board config level for cache handling code. The ARM Cortex-A7 has a dcache line size of 64 bytes. Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
15 lines
199 B
C
15 lines
199 B
C
/*
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* (C) Copyright 2012,2015 Stephen Warren
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#include "rpi-common.h"
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#endif
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