mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
299 lines
9.5 KiB
C
299 lines
9.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
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*
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* Dave Liu <daveliu@freescale.com>
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* based on source code of Shlomi Gridish
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*/
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#ifndef __QE_H__
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#define __QE_H__
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#include "common.h"
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#ifdef CONFIG_U_QE
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#include <linux/immap_qe.h>
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#endif
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#define QE_NUM_OF_BRGS 16
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#define UCC_MAX_NUM 8
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#define QE_DATAONLY_BASE 0
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#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE)
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/* QE threads SNUM
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*/
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typedef enum qe_snum_state {
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QE_SNUM_STATE_USED, /* used */
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QE_SNUM_STATE_FREE /* free */
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} qe_snum_state_e;
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typedef struct qe_snum {
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u8 num; /* snum */
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qe_snum_state_e state; /* state */
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} qe_snum_t;
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/* QE RISC allocation
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*/
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#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
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#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
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#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
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#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
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#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
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QE_RISC_ALLOCATION_RISC2)
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#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
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QE_RISC_ALLOCATION_RISC2 | \
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QE_RISC_ALLOCATION_RISC3 | \
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QE_RISC_ALLOCATION_RISC4)
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/* QE CECR commands for UCC fast.
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*/
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#define QE_CR_FLG 0x00010000
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#define QE_RESET 0x80000000
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#define QE_INIT_TX_RX 0x00000000
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#define QE_INIT_RX 0x00000001
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#define QE_INIT_TX 0x00000002
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#define QE_ENTER_HUNT_MODE 0x00000003
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#define QE_STOP_TX 0x00000004
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#define QE_GRACEFUL_STOP_TX 0x00000005
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#define QE_RESTART_TX 0x00000006
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#define QE_SWITCH_COMMAND 0x00000007
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#define QE_SET_GROUP_ADDRESS 0x00000008
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#define QE_INSERT_CELL 0x00000009
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#define QE_ATM_TRANSMIT 0x0000000a
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#define QE_CELL_POOL_GET 0x0000000b
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#define QE_CELL_POOL_PUT 0x0000000c
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#define QE_IMA_HOST_CMD 0x0000000d
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#define QE_ATM_MULTI_THREAD_INIT 0x00000011
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#define QE_ASSIGN_PAGE 0x00000012
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#define QE_START_FLOW_CONTROL 0x00000014
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#define QE_STOP_FLOW_CONTROL 0x00000015
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#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
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#define QE_GRACEFUL_STOP_RX 0x0000001a
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#define QE_RESTART_RX 0x0000001b
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/* QE CECR Sub Block Code - sub block code of QE command.
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*/
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#define QE_CR_SUBBLOCK_INVALID 0x00000000
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#define QE_CR_SUBBLOCK_USB 0x03200000
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#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
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#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
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#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
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#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
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#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
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#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
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#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
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#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
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#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
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#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
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#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
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#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
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#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
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#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
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#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
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#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
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#define QE_CR_SUBBLOCK_MCC1 0x03800000
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#define QE_CR_SUBBLOCK_MCC2 0x03a00000
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#define QE_CR_SUBBLOCK_MCC3 0x03000000
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#define QE_CR_SUBBLOCK_IDMA1 0x02800000
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#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
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#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
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#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
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#define QE_CR_SUBBLOCK_HPAC 0x01e00000
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#define QE_CR_SUBBLOCK_SPI1 0x01400000
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#define QE_CR_SUBBLOCK_SPI2 0x01600000
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#define QE_CR_SUBBLOCK_RAND 0x01c00000
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#define QE_CR_SUBBLOCK_TIMER 0x01e00000
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#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
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/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command.
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*/
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#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
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#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
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#define QE_CR_PROTOCOL_ATM_POS 0x0A
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#define QE_CR_PROTOCOL_ETHERNET 0x0C
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#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
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#define QE_CR_PROTOCOL_SHIFT 6
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/* QE ASSIGN PAGE command
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*/
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#define QE_CR_ASSIGN_PAGE_SNUM_SHIFT 17
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/* Communication Direction.
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*/
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typedef enum comm_dir {
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COMM_DIR_NONE = 0,
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COMM_DIR_RX = 1,
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COMM_DIR_TX = 2,
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COMM_DIR_RX_AND_TX = 3
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} comm_dir_e;
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/* Clocks and BRG's
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*/
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typedef enum qe_clock {
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QE_CLK_NONE = 0,
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QE_BRG1, /* Baud Rate Generator 1 */
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QE_BRG2, /* Baud Rate Generator 2 */
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QE_BRG3, /* Baud Rate Generator 3 */
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QE_BRG4, /* Baud Rate Generator 4 */
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QE_BRG5, /* Baud Rate Generator 5 */
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QE_BRG6, /* Baud Rate Generator 6 */
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QE_BRG7, /* Baud Rate Generator 7 */
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QE_BRG8, /* Baud Rate Generator 8 */
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QE_BRG9, /* Baud Rate Generator 9 */
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QE_BRG10, /* Baud Rate Generator 10 */
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QE_BRG11, /* Baud Rate Generator 11 */
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QE_BRG12, /* Baud Rate Generator 12 */
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QE_BRG13, /* Baud Rate Generator 13 */
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QE_BRG14, /* Baud Rate Generator 14 */
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QE_BRG15, /* Baud Rate Generator 15 */
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QE_BRG16, /* Baud Rate Generator 16 */
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QE_CLK1, /* Clock 1 */
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QE_CLK2, /* Clock 2 */
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QE_CLK3, /* Clock 3 */
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QE_CLK4, /* Clock 4 */
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QE_CLK5, /* Clock 5 */
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QE_CLK6, /* Clock 6 */
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QE_CLK7, /* Clock 7 */
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QE_CLK8, /* Clock 8 */
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QE_CLK9, /* Clock 9 */
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QE_CLK10, /* Clock 10 */
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QE_CLK11, /* Clock 11 */
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QE_CLK12, /* Clock 12 */
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QE_CLK13, /* Clock 13 */
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QE_CLK14, /* Clock 14 */
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QE_CLK15, /* Clock 15 */
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QE_CLK16, /* Clock 16 */
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QE_CLK17, /* Clock 17 */
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QE_CLK18, /* Clock 18 */
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QE_CLK19, /* Clock 19 */
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QE_CLK20, /* Clock 20 */
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QE_CLK21, /* Clock 21 */
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QE_CLK22, /* Clock 22 */
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QE_CLK23, /* Clock 23 */
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QE_CLK24, /* Clock 24 */
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QE_CLK_DUMMY
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} qe_clock_e;
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/* QE CMXGCR register
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*/
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#define QE_CMXGCR_MII_ENET_MNG_MASK 0x00007000
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#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
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/* QE CMXUCR registers
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*/
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#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
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/* QE BRG configuration register
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*/
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#define QE_BRGC_ENABLE 0x00010000
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#define QE_BRGC_DIVISOR_SHIFT 1
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#define QE_BRGC_DIVISOR_MAX 0xFFF
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#define QE_BRGC_DIV16 1
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/* QE SDMA registers
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*/
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#define QE_SDSR_BER1 0x02000000
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#define QE_SDSR_BER2 0x01000000
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#define QE_SDMR_GLB_1_MSK 0x80000000
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#define QE_SDMR_ADR_SEL 0x20000000
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#define QE_SDMR_BER1_MSK 0x02000000
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#define QE_SDMR_BER2_MSK 0x01000000
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#define QE_SDMR_EB1_MSK 0x00800000
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#define QE_SDMR_ER1_MSK 0x00080000
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#define QE_SDMR_ER2_MSK 0x00040000
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#define QE_SDMR_CEN_MASK 0x0000E000
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#define QE_SDMR_SBER_1 0x00000200
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#define QE_SDMR_SBER_2 0x00000200
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#define QE_SDMR_EB1_PR_MASK 0x000000C0
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#define QE_SDMR_ER1_PR 0x00000008
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#define QE_SDMR_CEN_SHIFT 13
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#define QE_SDMR_EB1_PR_SHIFT 6
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#define QE_SDTM_MSNUM_SHIFT 24
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#define QE_SDEBCR_BA_MASK 0x01FFFFFF
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/* Communication Processor */
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#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
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#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
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#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
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/* I-RAM */
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#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
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#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
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#define QE_IRAM_READY 0x80000000
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/* Structure that defines QE firmware binary files.
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*
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* See doc/README.qe_firmware for a description of these fields.
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*/
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struct qe_firmware {
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struct qe_header {
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u32 length; /* Length of the entire structure, in bytes */
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u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
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u8 version; /* Version of this layout. First ver is '1' */
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} header;
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u8 id[62]; /* Null-terminated identifier string */
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u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
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u8 count; /* Number of microcode[] structures */
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struct {
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u16 model; /* The SOC model */
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u8 major; /* The SOC revision major */
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u8 minor; /* The SOC revision minor */
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} __attribute__ ((packed)) soc;
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u8 padding[4]; /* Reserved, for alignment */
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u64 extended_modes; /* Extended modes */
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u32 vtraps[8]; /* Virtual trap addresses */
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u8 reserved[4]; /* Reserved, for future expansion */
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struct qe_microcode {
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u8 id[32]; /* Null-terminated identifier */
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u32 traps[16]; /* Trap addresses, 0 == ignore */
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u32 eccr; /* The value for the ECCR register */
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u32 iram_offset;/* Offset into I-RAM for the code */
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u32 count; /* Number of 32-bit words of the code */
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u32 code_offset;/* Offset of the actual microcode */
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u8 major; /* The microcode version major */
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u8 minor; /* The microcode version minor */
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u8 revision; /* The microcode version revision */
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u8 padding; /* Reserved, for alignment */
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u8 reserved[4]; /* Reserved, for future expansion */
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} __attribute__ ((packed)) microcode[1];
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/* All microcode binaries should be located here */
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/* CRC32 should be located here, after the microcode binaries */
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} __attribute__ ((packed));
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struct qe_firmware_info {
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char id[64]; /* Firmware name */
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u32 vtraps[8]; /* Virtual trap addresses */
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u64 extended_modes; /* Extended modes */
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};
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void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign);
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void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data);
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uint qe_muram_alloc(uint size, uint align);
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void *qe_muram_addr(uint offset);
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int qe_get_snum(void);
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void qe_put_snum(u8 snum);
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void qe_init(uint qe_base);
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void qe_reset(void);
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void qe_assign_page(uint snum, uint para_ram_base);
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int qe_set_brg(uint brg, uint rate);
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int qe_set_mii_clk_src(int ucc_num);
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int qe_upload_firmware(const struct qe_firmware *firmware);
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struct qe_firmware_info *qe_get_firmware_info(void);
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void ft_qe_setup(void *blob);
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void qe_init(uint qe_base);
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void qe_reset(void);
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#ifdef CONFIG_U_QE
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void u_qe_init(void);
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int u_qe_upload_firmware(const struct qe_firmware *firmware);
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void u_qe_resume(void);
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int u_qe_firmware_resume(const struct qe_firmware *firmware,
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qe_map_t *qe_immrr);
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#endif
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#endif /* __QE_H__ */
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