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![Simon Glass](/assets/img/avatar_default.png)
The Intel GPIO binding allows GPIOs to be globally numbered, so that it does not matter which GPIO bank is specified in the device tree. This is convenient and avoid confusion since the banks do not have the same number of GPIOs and the numbering is not sequential. The GPIO uclass ensures that the device mentioned in the devicetree binding is probed. It is fine for the driver to update gpio_desc to point to a different driver, but this may not have been probed. If it has not been, then it cannot be claimed since there is no uclass data. We could handle this in the GPIO uclass but so far it is an unusual situation so it is probably not worth the extra code. Handle this case in the GPIO driver by probing the selected device if necessary. Signed-off-by: Simon Glass <sjg@chromium.org>
222 lines
5.6 KiB
C
222 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 Google LLC
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*/
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#define LOG_CATEGORY UCLASS_GPIO
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <log.h>
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#include <p2sb.h>
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#include <pch.h>
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#include <pci.h>
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#include <syscon.h>
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#include <acpi/acpi_device.h>
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#include <asm/cpu.h>
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#include <asm/gpio.h>
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#include <asm/intel_pinctrl.h>
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#include <asm/intel_pinctrl_defs.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/arch/gpio.h>
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#include <dm/acpi.h>
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#include <dm/device-internal.h>
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#include <dt-bindings/gpio/x86-gpio.h>
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static int intel_gpio_get_value(struct udevice *dev, uint offset)
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{
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struct udevice *pinctrl = dev_get_parent(dev);
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uint mode, rx_tx;
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u32 reg;
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reg = intel_pinctrl_get_config_reg(pinctrl, offset);
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mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
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if (!mode) {
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rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
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if (rx_tx == PAD_CFG0_TX_DISABLE)
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return reg & PAD_CFG0_RX_STATE ? 1 : 0;
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else if (rx_tx == PAD_CFG0_RX_DISABLE)
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return reg & PAD_CFG0_TX_STATE ? 1 : 0;
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}
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return 0;
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}
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static int intel_gpio_set_value(struct udevice *dev, unsigned int offset,
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int value)
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{
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struct udevice *pinctrl = dev_get_parent(dev);
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uint config_offset;
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config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset);
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pcr_clrsetbits32(pinctrl, config_offset, PAD_CFG0_TX_STATE,
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value ? PAD_CFG0_TX_STATE : 0);
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return 0;
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}
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static int intel_gpio_get_function(struct udevice *dev, uint offset)
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{
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struct udevice *pinctrl = dev_get_parent(dev);
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uint mode, rx_tx;
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u32 reg;
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reg = intel_pinctrl_get_config_reg(pinctrl, offset);
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mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
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if (!mode) {
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rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
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if (rx_tx == PAD_CFG0_TX_DISABLE)
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return GPIOF_INPUT;
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else if (rx_tx == PAD_CFG0_RX_DISABLE)
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return GPIOF_OUTPUT;
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}
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return GPIOF_FUNC;
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}
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static int intel_gpio_xlate(struct udevice *orig_dev, struct gpio_desc *desc,
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struct ofnode_phandle_args *args)
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{
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struct udevice *pinctrl, *dev;
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int gpio, ret;
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/*
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* GPIO numbers are global in the device tree so it doesn't matter
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* which @orig_dev is used
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*/
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gpio = args->args[0];
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ret = intel_pinctrl_get_pad(gpio, &pinctrl, &desc->offset);
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if (ret)
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return log_msg_ret("bad", ret);
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device_find_first_child(pinctrl, &dev);
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if (!dev)
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return log_msg_ret("no child", -ENOENT);
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desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
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desc->dev = dev;
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/*
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* Handle the case where the wrong GPIO device was provided, since this
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* will not have been probed by the GPIO uclass before calling here
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* (see gpio_request_tail()).
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*/
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if (orig_dev != dev) {
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ret = device_probe(dev);
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if (ret)
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return log_msg_ret("probe", ret);
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}
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return 0;
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}
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static int intel_gpio_set_flags(struct udevice *dev, unsigned int offset,
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ulong flags)
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{
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struct udevice *pinctrl = dev_get_parent(dev);
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u32 bic0 = 0, bic1 = 0;
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u32 or0, or1;
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uint config_offset;
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config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset);
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if (flags & GPIOD_IS_OUT) {
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bic0 |= PAD_CFG0_MODE_MASK | PAD_CFG0_RX_STATE |
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PAD_CFG0_TX_DISABLE;
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or0 |= PAD_CFG0_MODE_GPIO | PAD_CFG0_RX_DISABLE;
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} else if (flags & GPIOD_IS_IN) {
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bic0 |= PAD_CFG0_MODE_MASK | PAD_CFG0_TX_STATE |
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PAD_CFG0_RX_DISABLE;
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or0 |= PAD_CFG0_MODE_GPIO | PAD_CFG0_TX_DISABLE;
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}
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if (flags & GPIOD_PULL_UP) {
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bic1 |= PAD_CFG1_PULL_MASK;
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or1 |= PAD_CFG1_PULL_UP_20K;
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} else if (flags & GPIOD_PULL_DOWN) {
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bic1 |= PAD_CFG1_PULL_MASK;
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or1 |= PAD_CFG1_PULL_DN_20K;
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}
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pcr_clrsetbits32(pinctrl, PAD_CFG0_OFFSET(config_offset), bic0, or0);
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pcr_clrsetbits32(pinctrl, PAD_CFG1_OFFSET(config_offset), bic1, or1);
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log_debug("%s: flags=%lx, offset=%x, config_offset=%x, %x/%x %x/%x\n",
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dev->name, flags, offset, config_offset, bic0, or0, bic1, or1);
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return 0;
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}
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#if CONFIG_IS_ENABLED(ACPIGEN)
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static int intel_gpio_get_acpi(const struct gpio_desc *desc,
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struct acpi_gpio *gpio)
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{
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struct udevice *pinctrl;
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int ret;
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if (!dm_gpio_is_valid(desc))
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return -ENOENT;
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pinctrl = dev_get_parent(desc->dev);
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memset(gpio, '\0', sizeof(*gpio));
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gpio->type = ACPI_GPIO_TYPE_IO;
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gpio->pull = ACPI_GPIO_PULL_DEFAULT;
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gpio->io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT;
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gpio->polarity = ACPI_GPIO_ACTIVE_HIGH;
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gpio->pin_count = 1;
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gpio->pins[0] = intel_pinctrl_get_acpi_pin(pinctrl, desc->offset);
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gpio->pin0_addr = intel_pinctrl_get_config_reg_addr(pinctrl,
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desc->offset);
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ret = acpi_get_path(pinctrl, gpio->resource, sizeof(gpio->resource));
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if (ret)
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return log_msg_ret("resource", ret);
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return 0;
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}
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#endif
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static int intel_gpio_probe(struct udevice *dev)
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{
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return 0;
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}
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static int intel_gpio_of_to_plat(struct udevice *dev)
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{
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struct gpio_dev_priv *upriv = dev_get_uclass_priv(dev);
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struct intel_pinctrl_priv *pinctrl_priv = dev_get_priv(dev->parent);
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const struct pad_community *comm = pinctrl_priv->comm;
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upriv->gpio_count = comm->last_pad - comm->first_pad + 1;
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upriv->bank_name = dev->name;
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return 0;
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}
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static const struct dm_gpio_ops gpio_intel_ops = {
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.get_value = intel_gpio_get_value,
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.set_value = intel_gpio_set_value,
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.get_function = intel_gpio_get_function,
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.xlate = intel_gpio_xlate,
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.set_flags = intel_gpio_set_flags,
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#if CONFIG_IS_ENABLED(ACPIGEN)
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.get_acpi = intel_gpio_get_acpi,
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#endif
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};
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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static const struct udevice_id intel_intel_gpio_ids[] = {
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{ .compatible = "intel,gpio" },
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{ }
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};
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#endif
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U_BOOT_DRIVER(intel_gpio) = {
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.name = "intel_gpio",
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.id = UCLASS_GPIO,
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.of_match = of_match_ptr(intel_intel_gpio_ids),
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.ops = &gpio_intel_ops,
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.of_to_plat = intel_gpio_of_to_plat,
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.probe = intel_gpio_probe,
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};
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