mirror of
https://github.com/brain-hackers/u-boot-brain
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6d7b061af1
Add P3060 SoC specific information:cores setup, LIODN setup, etc The P3060 SoC combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
110 lines
3.4 KiB
C
110 lines
3.4 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <phy.h>
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#include <fm_eth.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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u32 port_to_devdisr[] = {
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[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
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[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
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[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
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[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
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[FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
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[FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
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[FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
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[FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
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};
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static int is_device_disabled(enum fm_port port)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 devdisr2 = in_be32(&gur->devdisr2);
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return port_to_devdisr[port] & devdisr2;
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}
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void fman_disable_port(enum fm_port port)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
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}
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phy_interface_t fman_port_enet_if(enum fm_port port)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
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u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
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if (is_device_disabled(port))
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return PHY_INTERFACE_MODE_NONE;
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/* handle RGMII/MII first */
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if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
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FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1))
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return PHY_INTERFACE_MODE_RGMII;
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if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
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FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2))
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return PHY_INTERFACE_MODE_RGMII;
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if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
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FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))
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return PHY_INTERFACE_MODE_RGMII;
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if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1_EXT) ==
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FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII))
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return PHY_INTERFACE_MODE_RGMII;
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if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1_EXT) ==
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FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII))
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return PHY_INTERFACE_MODE_MII;
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if ((port == FM2_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2_EXT) ==
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FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII))
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return PHY_INTERFACE_MODE_RGMII;
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if ((port == FM2_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2_EXT) ==
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FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII))
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return PHY_INTERFACE_MODE_MII;
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switch (port) {
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case FM1_DTSEC1:
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case FM1_DTSEC2:
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case FM1_DTSEC3:
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case FM1_DTSEC4:
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if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
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return PHY_INTERFACE_MODE_SGMII;
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break;
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case FM2_DTSEC1:
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case FM2_DTSEC2:
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case FM2_DTSEC3:
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case FM2_DTSEC4:
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if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
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return PHY_INTERFACE_MODE_SGMII;
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break;
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default:
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return PHY_INTERFACE_MODE_NONE;
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}
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return PHY_INTERFACE_MODE_NONE;
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}
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