mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
177 lines
4.7 KiB
C
177 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2012 Keymile AG
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* Gerlando Falauto <gerlando.falauto@keymile.com>
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*
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* Based on km8321-common.h, see respective copyright notice for credits
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*/
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#ifndef __CONFIG_KM8309_COMMON_H
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#define __CONFIG_KM8309_COMMON_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 family */
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#define CONFIG_QE 1 /* Has QE */
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#define CONFIG_MPC830x 1 /* MPC830x family */
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#define CONFIG_MPC8309 1 /* MPC8309 CPU specific */
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#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
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/* include common defines/options for all 83xx Keymile boards */
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#include "km83xx-common.h"
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/* QE microcode/firmware address */
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#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
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/* between the u-boot partition and env */
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#ifndef CONFIG_SYS_QE_FW_ADDR
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#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000
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#endif
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/*
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* System IO Config
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*/
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/* 0x14000180 SICR_1 */
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#define CONFIG_SYS_SICRL (0 \
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| SICR_1_UART1_UART1RTS \
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| SICR_1_I2C_CKSTOP \
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| SICR_1_IRQ_A_IRQ \
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| SICR_1_IRQ_B_IRQ \
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| SICR_1_GPIO_A_GPIO \
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| SICR_1_GPIO_B_GPIO \
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| SICR_1_GPIO_C_GPIO \
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| SICR_1_GPIO_D_GPIO \
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| SICR_1_GPIO_E_GPIO \
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| SICR_1_GPIO_F_GPIO \
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| SICR_1_USB_A_UART2S \
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| SICR_1_USB_B_UART2RTS \
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| SICR_1_FEC1_FEC1 \
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| SICR_1_FEC2_FEC2 \
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)
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/* 0x00080400 SICR_2 */
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#define CONFIG_SYS_SICRH (0 \
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| SICR_2_FEC3_FEC3 \
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| SICR_2_HDLC1_A_HDLC1 \
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| SICR_2_ELBC_A_LA \
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| SICR_2_ELBC_B_LCLK \
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| SICR_2_HDLC2_A_HDLC2 \
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| SICR_2_USB_D_GPIO \
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| SICR_2_PCI_PCI \
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| SICR_2_HDLC1_B_HDLC1 \
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| SICR_2_HDLC1_C_HDLC1 \
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| SICR_2_HDLC2_B_GPIO \
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| SICR_2_HDLC2_C_HDLC2 \
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| SICR_2_QUIESCE_B \
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)
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/* GPR_1 */
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#define CONFIG_SYS_GPR1 0x50008060
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#define CONFIG_SYS_GP1DIR 0x00000000
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#define CONFIG_SYS_GP1ODR 0x00000000
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#define CONFIG_SYS_GP2DIR 0xFF000000
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#define CONFIG_SYS_GP2ODR 0x00000000
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/*
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* Hardware Reset Configuration Word
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*/
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#define CONFIG_SYS_HRCW_LOW (\
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HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
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HRCWL_DDR_TO_SCB_CLK_2X1 | \
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HRCWL_CSB_TO_CLKIN_2X1 | \
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HRCWL_CORE_TO_CSB_2X1 | \
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HRCWL_CE_PLL_VCO_DIV_2 | \
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HRCWL_CE_TO_PLL_1X3)
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#define CONFIG_SYS_HRCW_HIGH (\
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HRCWH_PCI_AGENT | \
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HRCWH_PCI_ARBITER_DISABLE | \
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HRCWH_CORE_ENABLE | \
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HRCWH_FROM_0X00000100 | \
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HRCWH_BOOTSEQ_DISABLE | \
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HRCWH_SW_WATCHDOG_DISABLE | \
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HRCWH_ROM_LOC_LOCAL_16BIT | \
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HRCWH_BIG_ENDIAN | \
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HRCWH_LALE_NORMAL)
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#define CONFIG_SYS_DDRCDR (\
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DDRCDR_EN | \
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DDRCDR_PZ_MAXZ | \
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DDRCDR_NZ_MAXZ | \
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DDRCDR_M_ODR)
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
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#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
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SDRAM_CFG_32_BE | \
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SDRAM_CFG_SREN | \
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SDRAM_CFG_HSE)
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
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#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
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(0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
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CSCONFIG_ODT_RD_NEVER | \
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CSCONFIG_ODT_WR_ONLY_CURRENT | \
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CSCONFIG_ROW_BIT_13 | \
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CSCONFIG_COL_BIT_10)
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#define CONFIG_SYS_DDR_MODE 0x47860242
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#define CONFIG_SYS_DDR_MODE2 0x8080c000
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#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
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(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
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(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
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(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
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(0 << TIMING_CFG0_WWT_SHIFT) | \
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(0 << TIMING_CFG0_RRT_SHIFT) | \
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(0 << TIMING_CFG0_WRT_SHIFT) | \
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(0 << TIMING_CFG0_RWT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
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(2 << TIMING_CFG1_WRTORD_SHIFT) | \
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(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
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(3 << TIMING_CFG1_WRREC_SHIFT) | \
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(7 << TIMING_CFG1_REFREC_SHIFT) | \
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(3 << TIMING_CFG1_ACTTORW_SHIFT) | \
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(7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
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(3 << TIMING_CFG1_PRETOACT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
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(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
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(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
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(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
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(3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
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(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
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(5 << TIMING_CFG2_CPO_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
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#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
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/* EEprom support */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LCRR_DBYP 0x80000000
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#define CONFIG_SYS_LCRR_EADC 0x00010000
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#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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/*
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* MMU Setup
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*/
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#define CONFIG_SYS_IBAT7L (0)
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#define CONFIG_SYS_IBAT7U (0)
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#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
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#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
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#endif /* __CONFIG_KM8309_COMMON_H */
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