mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-22 19:09:43 +09:00
e519f03a18
There is no real need to exactly define space for saving patterns for alternate memory test. It is much easier to allocate space on the stack and use it instead of trying to find out space where pattern should be saved. For example if you want to test the whole DDR memory you can't save patter to DDR and you need to find it out. On Xilinx devices DDR or OCM addresses were chosen but that means that OCM needs to be mapped and U-Boot has access permission there. It is easier to remove this limitation and simply save it on stack because it is very clear that memory test can't rewrite U-Boot and U-Boot has also full access to memory where runs from. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de>
83 lines
2.3 KiB
C
83 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuation settings for the sh7757lcr board
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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*/
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#ifndef __SH7757LCR_H
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#define __SH7757LCR_H
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#define CONFIG_CPU_SH7757 1
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#define CONFIG_SH7757LCR_DDR_ECC 1
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#define CONFIG_DISPLAY_BOARDINFO
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/* MEMORY */
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#define SH7757LCR_SDRAM_BASE (0x80000000)
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#define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024)
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#define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
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#define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)
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#define CONFIG_SYS_PBSIZE 256
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
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/* SCIF */
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#define CONFIG_CONS_SCIF2 1
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#define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
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224 * 1024 * 1024)
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE
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#define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE)
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#define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
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(128 + 16) * 1024 * 1024)
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#define CONFIG_SYS_MONITOR_BASE 0x00000000
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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/* Ether */
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 1
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#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
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#define CONFIG_BITBANGMII_MULTI
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
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#define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
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#define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024)
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#define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI
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#define SH7757LCR_ETHERNET_MAC_SIZE 17
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#define SH7757LCR_ETHERNET_NUM_CH 2
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/* Gigabit Ether */
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#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
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/* SPI */
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#define CONFIG_SH_SPI_BASE 0xfe002000
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/* MMCIF */
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#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
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#define CONFIG_SH_MMCIF_CLK 48000000
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/* SH7757 board */
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#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
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#define SH7757LCR_GRA_OFFSET 0x1f000000
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#define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
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#define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024)
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#define SH7757LCR_PCIEBRG_ADDR 0x00090000
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#define SH7757LCR_PCIEBRG_SIZE (96 * 1024)
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/* ENV setting */
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#define CONFIG_ENV_OVERWRITE 1
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netboot=bootp; bootm\0"
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 48000000
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#endif /* __SH7757LCR_H */
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