mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 18:56:15 +09:00
e519f03a18
There is no real need to exactly define space for saving patterns for alternate memory test. It is much easier to allocate space on the stack and use it instead of trying to find out space where pattern should be saved. For example if you want to test the whole DDR memory you can't save patter to DDR and you need to find it out. On Xilinx devices DDR or OCM addresses were chosen but that means that OCM needs to be mapped and U-Boot has access permission there. It is easier to remove this limitation and simply save it on stack because it is very clear that memory test can't rewrite U-Boot and U-Boot has also full access to memory where runs from. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de>
75 lines
2.0 KiB
C
75 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2020 Cortina Access Inc.
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*
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* Configuration for Cortina-Access Presidio board.
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*/
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#ifndef __PRESIDIO_ASIC_H
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#define __PRESIDIO_ASIC_H
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#define CONFIG_REMAKE_ELF
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#define CONFIG_SUPPORT_RAW_INITRD
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#define CONFIG_SYS_INIT_SP_ADDR 0x00100000
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#define CONFIG_SYS_BOOTM_LEN 0x00c00000
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY 25000000
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#define CONFIG_SYS_TIMER_RATE COUNTER_FREQUENCY
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#define CONFIG_SYS_TIMER_COUNTER 0xf4321008
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/* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE
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* does not yet support DT. Thus define it here.
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*/
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#define CONFIG_GICV2
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#define GICD_BASE 0xf7011000
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#define GICC_BASE 0xf7012000
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#define CONFIG_SYS_MEMTEST_START 0x05000000
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#define CONFIG_SYS_MEMTEST_END 0x0D000000
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
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#define CONFIG_SYS_TIMER_BASE 0xf4321000
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/* Use external clock source */
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#define PRESIDIO_APB_CLK 125000000
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#define CORTINA_PER_IO_FREQ PRESIDIO_APB_CLK
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/* Cortina Serial Configuration */
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#define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK)
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#define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \
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(void *)CONFIG_SYS_SERIAL1}
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_SERIAL0 PER_UART0_CFG
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#define CONFIG_SYS_SERIAL1 PER_UART1_CFG
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/* BOOTP options */
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#define CONFIG_BOOTP_BOOTFILESIZE
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LOAD_ADDR (DDR_BASE + 0x10000000)
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#define CONFIG_LAST_STAGE_INIT
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/* SDRAM Bank #1 */
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#define DDR_BASE 0x00000000
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#define PHYS_SDRAM_1 DDR_BASE
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#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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/* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* max command args */
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#define CONFIG_SYS_MAXARGS 64
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#define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0"
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#endif /* __PRESIDIO_ASIC_H */
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