mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-22 19:09:43 +09:00
e519f03a18
There is no real need to exactly define space for saving patterns for alternate memory test. It is much easier to allocate space on the stack and use it instead of trying to find out space where pattern should be saved. For example if you want to test the whole DDR memory you can't save patter to DDR and you need to find it out. On Xilinx devices DDR or OCM addresses were chosen but that means that OCM needs to be mapped and U-Boot has access permission there. It is easier to remove this limitation and simply save it on stack because it is very clear that memory test can't rewrite U-Boot and U-Boot has also full access to memory where runs from. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de>
87 lines
2.9 KiB
C
87 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuation settings for the Renesas Solutions Migo-R board
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*
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* Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*/
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#ifndef __MIGO_R_H
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#define __MIGO_R_H
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#define CONFIG_CPU_SH7722 1
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#define CONFIG_DISPLAY_BOARDINFO
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/* SMC9111 */
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#define CONFIG_SMC91111
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#define CONFIG_SMC91111_BASE (0xB0000000)
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/* MEMORY */
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#define MIGO_R_SDRAM_BASE (0x8C000000)
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#define MIGO_R_FLASH_BASE_1 (0xA0000000)
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#define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024)
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#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
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/* SCIF */
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#define CONFIG_CONS_SCIF0 1
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#define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
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/* Enable alternate, more extensive, memory test */
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/* Scratch address used by the alternate memory test */
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/* Enable temporary baudrate change while serial download */
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE
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#define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE)
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/* maybe more, but if so u-boot doesn't know about it... */
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#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
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/* default load address for scripts ?!? */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
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/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
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#define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1)
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/* Monitor size */
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#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
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/* Size of DRAM reserved for malloc() use */
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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/* FLASH */
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#undef CONFIG_SYS_FLASH_QUIET_TEST
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/* print 'E' for empty sector on flinfo */
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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/* Physical start address of Flash memory */
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#define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1)
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/* Max number of sectors on each Flash chip */
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#define CONFIG_SYS_MAX_FLASH_SECT 512
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/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
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/* Timeout for Flash erase operations (in ms) */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
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/* Timeout for Flash write operations (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
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/* Timeout for Flash set sector lock bit operations (in ms) */
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#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
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/* Timeout for Flash clear lock bit operations (in ms) */
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#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
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/* Use hardware flash sectors protection instead of U-Boot software protection */
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#undef CONFIG_SYS_DIRECT_FLASH_TFTP
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/* ENV setting */
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#define CONFIG_ENV_OVERWRITE 1
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/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#endif /* __MIGO_R_H */
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