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https://github.com/brain-hackers/u-boot-brain
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72a087e047
Patch by Haavard Skinnemoen, 06 Sep 2006 This patch adds support for the AT32AP CPU family and the AT32AP7000 chip, which is the first chip implementing the AVR32 architecture. The AT32AP CPU core is a high-performance implementation featuring a 7-stage pipeline, separate instruction- and data caches, and a MMU. For more information, please see the "AVR32 AP Technical Reference": http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf In addition to this, the AT32AP7000 chip comes with a large set of integrated peripherals, many of which are shared with the AT91 series of ARM-based microcontrollers from Atmel. Full data sheet is available here: http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
449 lines
8.7 KiB
C
449 lines
8.7 KiB
C
/*
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* Copyright (C) 2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/memory-map.h>
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#include <asm/arch/platform.h>
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#include "../sm.h"
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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const struct clock_domain chip_clock[] = {
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[CLOCK_CPU] = {
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.reg = SM_PM_CPU_MASK,
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.id = CLOCK_CPU,
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.bridge = NO_DEVICE,
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},
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[CLOCK_HSB] = {
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.reg = SM_PM_HSB_MASK,
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.id = CLOCK_HSB,
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.bridge = NO_DEVICE,
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},
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[CLOCK_PBA] = {
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.reg = SM_PM_PBA_MASK,
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.id = CLOCK_PBA,
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.bridge = DEVICE_PBA_BRIDGE,
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},
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[CLOCK_PBB] = {
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.reg = SM_PM_PBB_MASK,
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.id = CLOCK_PBB,
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.bridge = DEVICE_PBB_BRIDGE,
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},
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};
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static const struct resource hebi_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_HSB, 0 },
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},
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}, {
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_PBB, 13 },
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},
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}, {
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_PBB, 14 },
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},
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}, {
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.type = RESOURCE_GPIO,
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.u = {
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.gpio = { 27, DEVICE_PIOE, GPIO_FUNC_A, 0 },
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},
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},
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};
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static const struct resource pba_bridge_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_HSB, 1 },
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}
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}, {
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.type = RESOURCE_CLOCK,
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.u = {
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/* HSB-HSB Bridge */
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.clock = { CLOCK_HSB, 4 },
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},
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},
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};
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static const struct resource pbb_bridge_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_HSB, 2 },
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},
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},
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};
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static const struct resource hramc_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_HSB, 3 },
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},
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},
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};
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static const struct resource pioa_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_PBA, 10 },
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},
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},
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};
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static const struct resource piob_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_PBA, 11 },
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},
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},
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};
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static const struct resource pioc_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_PBA, 12 },
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},
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},
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};
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static const struct resource piod_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_PBA, 13 },
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},
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},
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};
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static const struct resource pioe_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_PBA, 14 },
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},
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},
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};
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static const struct resource sm_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_PBB, 0 },
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},
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},
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};
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static const struct resource intc_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_PBB, 1 },
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},
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},
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};
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static const struct resource hmatrix_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_PBB, 2 },
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},
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},
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};
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#if defined(CFG_HPDC)
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static const struct resource hpdc_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_PBA, 16 },
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},
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},
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};
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#endif
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#if defined(CFG_MACB0)
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static const struct resource macb0_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_HSB, 8 },
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},
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}, {
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_PBB, 6 },
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},
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}, {
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.type = RESOURCE_GPIO,
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.u = {
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.gpio = { 19, DEVICE_PIOC, GPIO_FUNC_A, 0 },
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},
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},
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};
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#endif
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#if defined(CFG_MACB1)
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static const struct resource macb1_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_HSB, 9 },
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},
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}, {
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_PBB, 7 },
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},
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}, {
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.type = RESOURCE_GPIO,
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.u = {
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.gpio = { 12, DEVICE_PIOC, GPIO_FUNC_B, 19 },
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},
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}, {
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.type = RESOURCE_GPIO,
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.u = {
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.gpio = { 14, DEVICE_PIOD, GPIO_FUNC_B, 2 },
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},
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},
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};
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#endif
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#if defined(CFG_LCDC)
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static const struct resource lcdc_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_HSB, 7 },
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},
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},
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};
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#endif
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#if defined(CFG_USART0)
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static const struct resource usart0_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_PBA, 3 },
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},
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}, {
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.type = RESOURCE_GPIO,
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.u = {
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.gpio = { 2, DEVICE_PIOA, GPIO_FUNC_B, 8 },
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},
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},
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};
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#endif
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#if defined(CFG_USART1)
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static const struct resource usart1_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_PBA, 4 },
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},
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}, {
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.type = RESOURCE_GPIO,
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.u = {
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.gpio = { 2, DEVICE_PIOA, GPIO_FUNC_A, 17 },
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},
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},
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};
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#endif
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#if defined(CFG_USART2)
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static const struct resource usart2_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_PBA, 5 },
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},
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}, {
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.type = RESOURCE_GPIO,
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.u = {
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.gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 26 },
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},
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},
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};
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#endif
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#if defined(CFG_USART3)
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static const struct resource usart3_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_PBA, 6 },
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},
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}, {
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.type = RESOURCE_GPIO,
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.u = {
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.gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 17 },
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},
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},
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};
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#endif
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#if defined(CFG_MMCI)
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static const struct resource mmci_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_PBB, 9 },
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},
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}, {
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.type = RESOURCE_GPIO,
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.u = {
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.gpio = { 6, DEVICE_PIOA, GPIO_FUNC_A, 10 },
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},
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},
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};
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#endif
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#if defined(CFG_DMAC)
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static const struct resource dmac_resource[] = {
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{
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.type = RESOURCE_CLOCK,
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.u = {
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.clock = { CLOCK_HSB, 10 },
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},
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},
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};
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#endif
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const struct device chip_device[] = {
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[DEVICE_HEBI] = {
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.regs = (void *)HSMC_BASE,
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.nr_resources = ARRAY_SIZE(hebi_resource),
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.resource = hebi_resource,
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},
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[DEVICE_PBA_BRIDGE] = {
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.nr_resources = ARRAY_SIZE(pba_bridge_resource),
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.resource = pba_bridge_resource,
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},
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[DEVICE_PBB_BRIDGE] = {
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.nr_resources = ARRAY_SIZE(pbb_bridge_resource),
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.resource = pbb_bridge_resource,
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},
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[DEVICE_HRAMC] = {
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.nr_resources = ARRAY_SIZE(hramc_resource),
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.resource = hramc_resource,
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},
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[DEVICE_PIOA] = {
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.regs = (void *)PIOA_BASE,
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.nr_resources = ARRAY_SIZE(pioa_resource),
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.resource = pioa_resource,
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},
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[DEVICE_PIOB] = {
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.regs = (void *)PIOB_BASE,
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.nr_resources = ARRAY_SIZE(piob_resource),
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.resource = piob_resource,
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},
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[DEVICE_PIOC] = {
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.regs = (void *)PIOC_BASE,
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.nr_resources = ARRAY_SIZE(pioc_resource),
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.resource = pioc_resource,
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},
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[DEVICE_PIOD] = {
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.regs = (void *)PIOD_BASE,
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.nr_resources = ARRAY_SIZE(piod_resource),
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.resource = piod_resource,
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},
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[DEVICE_PIOE] = {
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.regs = (void *)PIOE_BASE,
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.nr_resources = ARRAY_SIZE(pioe_resource),
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.resource = pioe_resource,
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},
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[DEVICE_SM] = {
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.regs = (void *)SM_BASE,
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.nr_resources = ARRAY_SIZE(sm_resource),
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.resource = sm_resource,
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},
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[DEVICE_INTC] = {
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.regs = (void *)INTC_BASE,
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.nr_resources = ARRAY_SIZE(intc_resource),
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.resource = intc_resource,
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},
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[DEVICE_HMATRIX] = {
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.regs = (void *)HMATRIX_BASE,
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.nr_resources = ARRAY_SIZE(hmatrix_resource),
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.resource = hmatrix_resource,
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},
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#if defined(CFG_HPDC)
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[DEVICE_HPDC] = {
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.nr_resources = ARRAY_SIZE(hpdc_resource),
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.resource = hpdc_resource,
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},
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#endif
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#if defined(CFG_MACB0)
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[DEVICE_MACB0] = {
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.regs = (void *)MACB0_BASE,
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.nr_resources = ARRAY_SIZE(macb0_resource),
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.resource = macb0_resource,
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},
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#endif
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#if defined(CFG_MACB1)
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[DEVICE_MACB1] = {
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.regs = (void *)MACB1_BASE,
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.nr_resources = ARRAY_SIZE(macb1_resource),
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.resource = macb1_resource,
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},
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#endif
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#if defined(CFG_LCDC)
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[DEVICE_LCDC] = {
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.nr_resources = ARRAY_SIZE(lcdc_resource),
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.resource = lcdc_resource,
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},
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#endif
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#if defined(CFG_USART0)
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[DEVICE_USART0] = {
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.regs = (void *)USART0_BASE,
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.nr_resources = ARRAY_SIZE(usart0_resource),
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.resource = usart0_resource,
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},
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#endif
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#if defined(CFG_USART1)
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[DEVICE_USART1] = {
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.regs = (void *)USART1_BASE,
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.nr_resources = ARRAY_SIZE(usart1_resource),
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.resource = usart1_resource,
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},
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#endif
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#if defined(CFG_USART2)
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[DEVICE_USART2] = {
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.regs = (void *)USART2_BASE,
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.nr_resources = ARRAY_SIZE(usart2_resource),
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.resource = usart2_resource,
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},
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#endif
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#if defined(CFG_USART3)
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[DEVICE_USART3] = {
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.regs = (void *)USART3_BASE,
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.nr_resources = ARRAY_SIZE(usart3_resource),
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.resource = usart3_resource,
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},
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#endif
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#if defined(CFG_MMCI)
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[DEVICE_MMCI] = {
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.regs = (void *)MMCI_BASE,
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.nr_resources = ARRAY_SIZE(mmci_resource),
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.resource = mmci_resource,
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},
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#endif
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#if defined(CFG_DMAC)
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[DEVICE_DMAC] = {
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.regs = (void *)DMAC_BASE,
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.nr_resources = ARRAY_SIZE(dmac_resource),
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.resource = dmac_resource,
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},
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#endif
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};
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