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https://github.com/brain-hackers/u-boot-brain
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2d0daa0361
This is needed because we will be possibly be locating devices at physical addresses above 32bits, and the asm preprocessing does not appear to deal with ULL constants properly. We now call write_bat in lib_ppc/bat_rw.c. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com>
149 lines
3.8 KiB
C
149 lines
3.8 KiB
C
/*
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* Copyright 2004 Freescale Semiconductor.
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* Jeff Brown
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* cpu_init.c - low level cpu init
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*/
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#include <config.h>
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#include <common.h>
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#include <mpc86xx.h>
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#include <asm/mmu.h>
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#include <asm/fsl_law.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Breathe some life into the CPU...
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*
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* Set up the memory map
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* initialize a bunch of registers
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*/
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void cpu_init_f(void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_lbc_t *memctl = &immap->im_lbc;
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
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/* Clear initial global data */
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memset ((void *) gd, 0, sizeof (gd_t));
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#ifdef CONFIG_FSL_LAW
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init_laws();
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#endif
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/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
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* addresses - these have to be modified later when FLASH size
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* has been determined
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*/
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#if defined(CFG_OR0_REMAP)
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memctl->or0 = CFG_OR0_REMAP;
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#endif
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#if defined(CFG_OR1_REMAP)
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memctl->or1 = CFG_OR1_REMAP;
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#endif
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/* now restrict to preliminary range */
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#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
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memctl->br0 = CFG_BR0_PRELIM;
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memctl->or0 = CFG_OR0_PRELIM;
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#endif
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#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
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memctl->or1 = CFG_OR1_PRELIM;
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memctl->br1 = CFG_BR1_PRELIM;
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#endif
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#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
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memctl->or2 = CFG_OR2_PRELIM;
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memctl->br2 = CFG_BR2_PRELIM;
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#endif
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#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
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memctl->or3 = CFG_OR3_PRELIM;
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memctl->br3 = CFG_BR3_PRELIM;
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#endif
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#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
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memctl->or4 = CFG_OR4_PRELIM;
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memctl->br4 = CFG_BR4_PRELIM;
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#endif
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#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
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memctl->or5 = CFG_OR5_PRELIM;
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memctl->br5 = CFG_BR5_PRELIM;
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#endif
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#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
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memctl->or6 = CFG_OR6_PRELIM;
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memctl->br6 = CFG_BR6_PRELIM;
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#endif
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#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
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memctl->or7 = CFG_OR7_PRELIM;
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memctl->br7 = CFG_BR7_PRELIM;
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#endif
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/* enable the timebase bit in HID0 */
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set_hid0(get_hid0() | 0x4000000);
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/* enable EMCP, SYNCBE | ABE bits in HID1 */
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set_hid1(get_hid1() | 0x80000C00);
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r(void)
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{
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return 0;
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}
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/* Set up BAT registers */
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void setup_bats(void)
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{
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write_bat(DBAT0, CFG_DBAT0U, CFG_DBAT0L);
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write_bat(IBAT0, CFG_IBAT0U, CFG_IBAT0L);
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write_bat(DBAT1, CFG_DBAT1U, CFG_DBAT1L);
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write_bat(IBAT1, CFG_IBAT1U, CFG_IBAT1L);
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write_bat(DBAT2, CFG_DBAT2U, CFG_DBAT2L);
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write_bat(IBAT2, CFG_IBAT2U, CFG_IBAT2L);
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write_bat(DBAT3, CFG_DBAT3U, CFG_DBAT3L);
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write_bat(IBAT3, CFG_IBAT3U, CFG_IBAT3L);
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write_bat(DBAT4, CFG_DBAT4U, CFG_DBAT4L);
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write_bat(IBAT4, CFG_IBAT4U, CFG_IBAT4L);
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write_bat(DBAT5, CFG_DBAT5U, CFG_DBAT5L);
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write_bat(IBAT5, CFG_IBAT5U, CFG_IBAT5L);
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write_bat(DBAT6, CFG_DBAT6U, CFG_DBAT6L);
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write_bat(IBAT6, CFG_IBAT6U, CFG_IBAT6L);
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write_bat(DBAT7, CFG_DBAT7U, CFG_DBAT7L);
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write_bat(IBAT7, CFG_IBAT7U, CFG_IBAT7L);
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return;
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}
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