64 lines
1.2 KiB
Plaintext
64 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* P2041 Silicon/SoC Device Tree Source (pre include)
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*
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* Copyright 2011 - 2015 Freescale Semiconductor Inc.
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* Copyright 2019 NXP
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*/
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/dts-v1/;
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/include/ "e500mc_power_isa.dtsi"
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/ {
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compatible = "fsl,P2041";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: PowerPC,e500mc@0 {
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device_type = "cpu";
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reg = <0>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu1: PowerPC,e500mc@1 {
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device_type = "cpu";
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reg = <1>;
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fsl,portid-mapping = <0x40000000>;
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};
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cpu2: PowerPC,e500mc@2 {
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device_type = "cpu";
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reg = <2>;
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fsl,portid-mapping = <0x20000000>;
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};
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cpu3: PowerPC,e500mc@3 {
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device_type = "cpu";
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reg = <3>;
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fsl,portid-mapping = <0x10000000>;
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};
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};
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soc: soc@ffe000000 {
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
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reg = <0xf 0xfe000000 0 0x00001000>;
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <4>;
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reg = <0x40000 0x40000>;
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compatible = "fsl,mpic", "chrp,open-pic";
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device_type = "open-pic";
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clock-frequency = <0x0>;
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};
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};
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};
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