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https://github.com/brain-hackers/u-boot-brain
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8331188615
Since there is now a new version of the FSP and it is incompatible with the existing version, move the code into an fsp1 directory. This will allow us to put FSP v2 code into an fsp2 directory. Add a Kconfig which defines which version is in use. Some of the code in this new fsp1/ directory is generic across both FSPv1 and FSPv2. Future patches will address this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
112 lines
2.8 KiB
C
112 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
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*/
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#ifndef _U_BOOT_I386_H_
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#define _U_BOOT_I386_H_ 1
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struct global_data;
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extern char gdt_rom[];
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/* cpu/.../cpu.c */
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int arch_cpu_init(void);
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/**
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* x86_cpu_init_f() - Set up basic features of the x86 CPU
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*
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* 0 on success, -ve on error
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*/
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int x86_cpu_init_f(void);
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/**
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* x86_cpu_reinit_f() - Set up the CPU a second time
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*
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* Once cpu_init_f() has been called (e.g. in SPL) we should not call it
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* again (e.g. in U-Boot proper) since it sets up the state from scratch.
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* Call this function in later phases of U-Boot instead. It reads the CPU
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* identify so that CPU functions can be used correctly, but does not change
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* anything.
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*
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* @return 0 (indicating success, to mimic cpu_init_f())
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*/
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int x86_cpu_reinit_f(void);
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int cpu_init_f(void);
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void setup_gdt(struct global_data *id, u64 *gdt_addr);
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/*
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* Setup FSP execution environment GDT to use the one we used in
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* arch/x86/cpu/start16.S and reload the segment registers.
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*/
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void setup_fsp_gdt(void);
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int init_cache(void);
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int cleanup_before_linux(void);
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/* cpu/.../timer.c */
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void timer_isr(void *);
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typedef void (timer_fnc_t) (void);
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int register_timer_isr (timer_fnc_t *isr_func);
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unsigned long get_tbclk_mhz(void);
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void timer_set_base(uint64_t base);
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int i8254_init(void);
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/* cpu/.../interrupts.c */
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int cpu_init_interrupts(void);
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int cleanup_before_linux(void);
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int x86_cleanup_before_linux(void);
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void x86_enable_caches(void);
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void x86_disable_caches(void);
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int x86_init_cache(void);
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ulong board_get_usable_ram_top(ulong total_size);
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int default_print_cpuinfo(void);
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/* Set up a UART which can be used with printch(), printhex8(), etc. */
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int setup_internal_uart(int enable);
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void setup_pcat_compatibility(void);
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void isa_unmap_rom(u32 addr);
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u32 isa_map_rom(u32 bus_addr, int size);
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/* arch/x86/lib/... */
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int video_bios_init(void);
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/* arch/x86/lib/fsp1,2/... */
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/**
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* fsp_save_s3_stack() - save stack address to CMOS for next S3 boot
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*
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* At the end of pre-relocation phase, save the new stack address
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* to CMOS and use it as the stack on next S3 boot for fsp_init()
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* continuation function.
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*
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* @return: 0 if OK, -ve on error
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*/
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int fsp_save_s3_stack(void);
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void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
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void board_init_f_r(void) __attribute__ ((noreturn));
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int arch_misc_init(void);
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/* Read the time stamp counter */
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static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void)
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{
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uint32_t high, low;
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__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high));
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return (((uint64_t)high) << 32) | low;
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}
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/* board/... */
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void timer_set_tsc_base(uint64_t new_base);
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uint64_t timer_get_tsc(void);
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void quick_ram_check(void);
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#define PCI_VGA_RAM_IMAGE_START 0xc0000
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#endif /* _U_BOOT_I386_H_ */
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