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![Prafulla Wadaskar](/assets/img/avatar_default.png)
Earlier Device Identification register was used to detect the type for SoC, considering 88F6282 support to be added, It is not possible to detect the same using current algorithm. With this patch, device ID is being read using PCIE devid register, also valid chip revision ID will also be read and displayed Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
400 lines
11 KiB
C
400 lines
11 KiB
C
/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/cache.h>
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#include <u-boot/md5.h>
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#include <asm/arch/kirkwood.h>
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#include <hush.h>
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#define BUFLEN 16
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void reset_cpu(unsigned long ignored)
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{
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struct kwcpu_registers *cpureg =
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(struct kwcpu_registers *)KW_CPU_REG_BASE;
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writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
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&cpureg->rstoutn_mask);
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writel(readl(&cpureg->sys_soft_rst) | 1,
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&cpureg->sys_soft_rst);
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while (1) ;
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}
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/*
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* Generates Ramdom hex number reading some time varient system registers
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* and using md5 algorithm
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*/
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unsigned char get_random_hex(void)
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{
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int i;
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u32 inbuf[BUFLEN];
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u8 outbuf[BUFLEN];
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/*
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* in case of 88F6281/88F6282/88F6192 A0,
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* Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
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* Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are
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* reserved regs and does not have names at this moment
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* (no errata available)
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*/
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writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
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for (i = 0; i < BUFLEN; i++) {
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inbuf[i] = readl(KW_REG_UNDOC_0x1470);
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}
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md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf);
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return outbuf[outbuf[7] % 0x0f];
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}
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/*
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* Window Size
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* Used with the Base register to set the address window size and location.
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* Must be programmed from LSB to MSB as sequence of ones followed by
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* sequence of zeros. The number of ones specifies the size of the window in
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* 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
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* NOTE: A value of 0x0 specifies 64-KByte size.
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*/
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unsigned int kw_winctrl_calcsize(unsigned int sizeval)
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{
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int i;
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unsigned int j = 0;
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u32 val = sizeval >> 1;
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for (i = 0; val >= 0x10000; i++) {
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j |= (1 << i);
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val = val >> 1;
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}
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return (0x0000ffff & j);
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}
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/*
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* kw_config_adr_windows - Configure address Windows
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*
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* There are 8 address windows supported by Kirkwood Soc to addess different
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* devices. Each window can be configured for size, BAR and remap addr
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* Below configuration is standard for most of the cases
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*
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* If remap function not used, remap_lo must be set as base
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*
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* Reference Documentation:
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* Mbus-L to Mbus Bridge Registers Configuration.
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* (Sec 25.1 and 25.3 of Datasheet)
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*/
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int kw_config_adr_windows(void)
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{
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struct kwwin_registers *winregs =
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(struct kwwin_registers *)KW_CPU_WIN_BASE;
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/* Window 0: PCIE MEM address space */
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writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
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KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
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writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
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writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
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writel(0x0, &winregs[0].remap_hi);
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/* Window 1: PCIE IO address space */
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writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
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KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
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writel(KW_DEFADR_PCI_IO, &winregs[1].base);
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writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
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writel(0x0, &winregs[1].remap_hi);
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/* Window 2: NAND Flash address space */
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writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
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KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
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writel(KW_DEFADR_NANDF, &winregs[2].base);
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writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
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writel(0x0, &winregs[2].remap_hi);
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/* Window 3: SPI Flash address space */
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writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
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KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
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writel(KW_DEFADR_SPIF, &winregs[3].base);
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writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
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writel(0x0, &winregs[3].remap_hi);
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/* Window 4: BOOT Memory address space */
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writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
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KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
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writel(KW_DEFADR_BOOTROM, &winregs[4].base);
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/* Window 5: Security SRAM address space */
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writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
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KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
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writel(KW_DEFADR_SASRAM, &winregs[5].base);
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/* Window 6-7: Disabled */
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writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
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writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
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return 0;
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}
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/*
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* kw_config_gpio - GPIO configuration
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*/
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void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
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{
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struct kwgpio_registers *gpio0reg =
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(struct kwgpio_registers *)KW_GPIO0_BASE;
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struct kwgpio_registers *gpio1reg =
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(struct kwgpio_registers *)KW_GPIO1_BASE;
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/* Init GPIOS to default values as per board requirement */
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writel(gpp0_oe_val, &gpio0reg->dout);
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writel(gpp1_oe_val, &gpio1reg->dout);
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writel(gpp0_oe, &gpio0reg->oe);
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writel(gpp1_oe, &gpio1reg->oe);
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}
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/*
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* kw_config_mpp - Multi-Purpose Pins Functionality configuration
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*
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* Each MPP can be configured to different functionality through
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* MPP control register, ref (sec 6.1 of kirkwood h/w specification)
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*
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* There are maximum 64 Multi-Pourpose Pins on Kirkwood
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* Each MPP functionality can be configuration by a 4bit value
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* of MPP control reg, the value and associated functionality depends
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* upon used SoC varient
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*/
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int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
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u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
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{
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u32 *mppreg = (u32 *) KW_MPP_BASE;
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/* program mpp registers */
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writel(mpp0_7, &mppreg[0]);
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writel(mpp8_15, &mppreg[1]);
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writel(mpp16_23, &mppreg[2]);
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writel(mpp24_31, &mppreg[3]);
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writel(mpp32_39, &mppreg[4]);
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writel(mpp40_47, &mppreg[5]);
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writel(mpp48_55, &mppreg[6]);
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return 0;
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}
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/*
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* SYSRSTn Duration Counter Support
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*
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* Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
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* When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
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* The SYSRSTn duration counter is useful for implementing a manufacturer
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* or factory reset. Upon a long reset assertion that is greater than a
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* pre-configured environment variable value for sysrstdelay,
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* The counter value is stored in the SYSRSTn Length Counter Register
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* The counter is based on the 25-MHz reference clock (40ns)
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* It is a 29-bit counter, yielding a maximum counting duration of
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* 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
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* it remains at this value until counter reset is triggered by setting
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* bit 31 of KW_REG_SYSRST_CNT
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*/
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static void kw_sysrst_action(void)
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{
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int ret;
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char *s = getenv("sysrstcmd");
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if (!s) {
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debug("Error.. %s failed, check sysrstcmd\n",
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__FUNCTION__);
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return;
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}
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debug("Starting %s process...\n", __FUNCTION__);
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#if !defined(CONFIG_SYS_HUSH_PARSER)
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ret = run_command (s, 0);
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#else
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ret = parse_string_outer(s, FLAG_PARSE_SEMICOLON
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| FLAG_EXIT_FROM_LOOP);
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#endif
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if (ret < 0)
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debug("Error.. %s failed\n", __FUNCTION__);
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else
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debug("%s process finished\n", __FUNCTION__);
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}
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static void kw_sysrst_check(void)
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{
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u32 sysrst_cnt, sysrst_dly;
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char *s;
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/*
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* no action if sysrstdelay environment variable is not defined
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*/
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s = getenv("sysrstdelay");
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if (s == NULL)
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return;
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/* read sysrstdelay value */
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sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
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/* read SysRst Length counter register (bits 28:0) */
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sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
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debug("H/w Rst hold time: %d.%d secs\n",
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sysrst_cnt / SYSRST_CNT_1SEC_VAL,
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sysrst_cnt % SYSRST_CNT_1SEC_VAL);
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/* clear the counter for next valid read*/
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writel(1 << 31, KW_REG_SYSRST_CNT);
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/*
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* sysrst_action:
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* if H/w Reset key is pressed and hold for time
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* more than sysrst_dly in seconds
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*/
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if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
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kw_sysrst_action();
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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char *rev;
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u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
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u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
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if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
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printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
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return -1;
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}
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switch (revid) {
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case 0:
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rev = "Z0";
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break;
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case 2:
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rev = "A0";
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break;
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case 3:
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rev = "A1";
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break;
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default:
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rev = "??";
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break;
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}
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printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
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return 0;
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}
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#endif /* CONFIG_DISPLAY_CPUINFO */
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#ifdef CONFIG_ARCH_CPU_INIT
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int arch_cpu_init(void)
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{
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u32 reg;
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struct kwcpu_registers *cpureg =
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(struct kwcpu_registers *)KW_CPU_REG_BASE;
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/* Linux expects` the internal registers to be at 0xf1000000 */
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writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
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/* Enable and invalidate L2 cache in write through mode */
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writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
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invalidate_l2_cache();
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kw_config_adr_windows();
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#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
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/*
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* Configures the I/O voltage of the pads connected to Egigabit
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* Ethernet interface to 1.8V
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* By defult it is set to 3.3V
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*/
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reg = readl(KW_REG_MPP_OUT_DRV_REG);
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reg |= (1 << 7);
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writel(reg, KW_REG_MPP_OUT_DRV_REG);
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#endif
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#ifdef CONFIG_KIRKWOOD_EGIGA_INIT
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/*
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* Set egiga port0/1 in normal functional mode
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* This is required becasue on kirkwood by default ports are in reset mode
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* OS egiga driver may not have provision to set them in normal mode
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* and if u-boot is build without network support, network may fail at OS level
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*/
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reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
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reg &= ~(1 << 4); /* Clear PortReset Bit */
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writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
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reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
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reg &= ~(1 << 4); /* Clear PortReset Bit */
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writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
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#endif
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#ifdef CONFIG_KIRKWOOD_PCIE_INIT
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/*
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* Enable PCI Express Port0
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*/
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reg = readl(&cpureg->ctrl_stat);
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reg |= (1 << 0); /* Set PEX0En Bit */
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writel(reg, &cpureg->ctrl_stat);
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#endif
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return 0;
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}
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#endif /* CONFIG_ARCH_CPU_INIT */
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/*
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* SOC specific misc init
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*/
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#if defined(CONFIG_ARCH_MISC_INIT)
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int arch_misc_init(void)
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{
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volatile u32 temp;
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/*CPU streaming & write allocate */
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temp = readfr_extra_feature_reg();
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temp &= ~(1 << 28); /* disable wr alloc */
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writefr_extra_feature_reg(temp);
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temp = readfr_extra_feature_reg();
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temp &= ~(1 << 29); /* streaming disabled */
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writefr_extra_feature_reg(temp);
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/* L2Cache settings */
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temp = readfr_extra_feature_reg();
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/* Disable L2C pre fetch - Set bit 24 */
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temp |= (1 << 24);
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/* enable L2C - Set bit 22 */
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temp |= (1 << 22);
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writefr_extra_feature_reg(temp);
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icache_enable();
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/* Change reset vector to address 0x0 */
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temp = get_cr();
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set_cr(temp & ~CR_V);
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/* checks and execute resset to factory event */
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kw_sysrst_check();
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return 0;
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}
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#endif /* CONFIG_ARCH_MISC_INIT */
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#ifdef CONFIG_MVGBE
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int cpu_eth_init(bd_t *bis)
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{
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mvgbe_initialize(bis);
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return 0;
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}
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#endif
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