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![Trent Piepho](/assets/img/avatar_default.png)
This can be used for device register access from board code. This allows access to capabilities in the RTC chip not abstracted in U-Boot's RTC class. E.g., device NVRAM or a tamper detection circuit. Cc: Klaus Goger <klaus.goger@theobroma-systems.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
198 lines
4.7 KiB
C
198 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2008
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* Tor Krill, Excito Elektronik i Skåne , tor@excito.com
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*
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* Modelled after the ds1337 driver
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*/
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/*
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* Date & Time support (no alarms) for Intersil
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* ISL1208 Real Time Clock (RTC).
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*/
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#include <common.h>
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#include <command.h>
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#include <dm.h>
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#include <rtc.h>
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#include <i2c.h>
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/*---------------------------------------------------------------------*/
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#ifdef DEBUG_RTC
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#define DEBUGR(fmt,args...) printf(fmt ,##args)
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#else
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#define DEBUGR(fmt,args...)
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#endif
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/*---------------------------------------------------------------------*/
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/*
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* RTC register addresses
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*/
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#define RTC_SEC_REG_ADDR 0x0
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#define RTC_MIN_REG_ADDR 0x1
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#define RTC_HR_REG_ADDR 0x2
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#define RTC_DATE_REG_ADDR 0x3
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#define RTC_MON_REG_ADDR 0x4
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#define RTC_YR_REG_ADDR 0x5
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#define RTC_DAY_REG_ADDR 0x6
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#define RTC_STAT_REG_ADDR 0x7
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/*
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* RTC control register bits
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*/
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/*
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* RTC status register bits
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*/
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#define RTC_STAT_BIT_ARST 0x80 /* AUTO RESET ENABLE BIT */
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#define RTC_STAT_BIT_XTOSCB 0x40 /* CRYSTAL OSCILLATOR ENABLE BIT */
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#define RTC_STAT_BIT_WRTC 0x10 /* WRITE RTC ENABLE BIT */
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#define RTC_STAT_BIT_ALM 0x04 /* ALARM BIT */
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#define RTC_STAT_BIT_BAT 0x02 /* BATTERY BIT */
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#define RTC_STAT_BIT_RTCF 0x01 /* REAL TIME CLOCK FAIL BIT */
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/*
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* Read an RTC register
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*/
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static int isl1208_rtc_read8(struct udevice *dev, unsigned int reg)
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{
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return dm_i2c_reg_read(dev, reg);
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}
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/*
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* Write an RTC register
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*/
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static int isl1208_rtc_write8(struct udevice *dev, unsigned int reg, int val)
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{
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return dm_i2c_reg_write(dev, reg, val);
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}
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/*
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* Get the current time from the RTC
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*/
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static int isl1208_rtc_get(struct udevice *dev, struct rtc_time *tmp)
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{
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int ret;
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uchar buf[8], val;
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ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
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if (ret < 0)
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return ret;
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if (buf[RTC_STAT_REG_ADDR] & RTC_STAT_BIT_RTCF) {
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printf ("### Warning: RTC oscillator has stopped\n");
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ret = dm_i2c_read(dev, RTC_STAT_REG_ADDR, &val, sizeof(val));
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if (ret < 0)
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return ret;
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val = val & ~(RTC_STAT_BIT_BAT | RTC_STAT_BIT_RTCF);
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ret = dm_i2c_write(dev, RTC_STAT_REG_ADDR, &val, sizeof(val));
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if (ret < 0)
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return ret;
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}
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tmp->tm_sec = bcd2bin(buf[RTC_SEC_REG_ADDR] & 0x7F);
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tmp->tm_min = bcd2bin(buf[RTC_MIN_REG_ADDR] & 0x7F);
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tmp->tm_hour = bcd2bin(buf[RTC_HR_REG_ADDR] & 0x3F);
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tmp->tm_mday = bcd2bin(buf[RTC_DATE_REG_ADDR] & 0x3F);
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tmp->tm_mon = bcd2bin(buf[RTC_MON_REG_ADDR] & 0x1F);
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tmp->tm_year = bcd2bin(buf[RTC_YR_REG_ADDR]) + 2000;
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tmp->tm_wday = bcd2bin(buf[RTC_DAY_REG_ADDR] & 0x07);
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tmp->tm_yday = 0;
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tmp->tm_isdst= 0;
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DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
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tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
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tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
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return 0;
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}
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/*
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* Set the RTC
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*/
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static int isl1208_rtc_set(struct udevice *dev, const struct rtc_time *tmp)
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{
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int ret;
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uchar val, buf[7];
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DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
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tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
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tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
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if (tmp->tm_year < 2000 || tmp->tm_year > 2099)
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printf("WARNING: year should be between 2000 and 2099!\n");
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/* enable write */
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ret = dm_i2c_read(dev, RTC_STAT_REG_ADDR, &val, sizeof(val));
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if (ret < 0)
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return ret;
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val = val | RTC_STAT_BIT_WRTC;
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ret = dm_i2c_write(dev, RTC_STAT_REG_ADDR, &val, sizeof(val));
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if (ret < 0)
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return ret;
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buf[RTC_YR_REG_ADDR] = bin2bcd(tmp->tm_year % 100);
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buf[RTC_MON_REG_ADDR] = bin2bcd(tmp->tm_mon);
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buf[RTC_DAY_REG_ADDR] = bin2bcd(tmp->tm_wday);
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buf[RTC_DATE_REG_ADDR] = bin2bcd(tmp->tm_mday);
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buf[RTC_HR_REG_ADDR] = bin2bcd(tmp->tm_hour) | 0x80; /* 24h clock */
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buf[RTC_MIN_REG_ADDR] = bin2bcd(tmp->tm_min);
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buf[RTC_SEC_REG_ADDR] = bin2bcd(tmp->tm_sec);
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ret = dm_i2c_write(dev, 0, buf, sizeof(buf));
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if (ret < 0)
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return ret;
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/* disable write */
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ret = dm_i2c_read(dev, RTC_STAT_REG_ADDR, &val, sizeof(val));
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if (ret < 0)
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return ret;
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val = val & ~RTC_STAT_BIT_WRTC;
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ret = dm_i2c_write(dev, RTC_STAT_REG_ADDR, &val, sizeof(val));
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if (ret < 0)
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return ret;
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return 0;
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}
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static int isl1208_rtc_reset(struct udevice *dev)
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{
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return 0;
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}
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static int isl1208_probe(struct udevice *dev)
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{
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i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS |
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DM_I2C_CHIP_WR_ADDRESS);
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return 0;
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}
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static const struct rtc_ops isl1208_rtc_ops = {
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.get = isl1208_rtc_get,
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.set = isl1208_rtc_set,
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.reset = isl1208_rtc_reset,
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.read8 = isl1208_rtc_read8,
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.write8 = isl1208_rtc_write8,
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};
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static const struct udevice_id isl1208_rtc_ids[] = {
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{ .compatible = "isil,isl1208" },
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{ }
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};
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U_BOOT_DRIVER(rtc_isl1208) = {
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.name = "rtc-isl1208",
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.id = UCLASS_RTC,
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.probe = isl1208_probe,
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.of_match = isl1208_rtc_ids,
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.ops = &isl1208_rtc_ops,
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};
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