mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 19:26:16 +09:00
e3b9c98a23
Update this driver to support driver model. As all MVEBU boards using
this driver are converted with this patch, the non-driver-model code
can be removed completely. This is also the reason why this patch
is quite big and includes a) the driver change and b) the
platform change. As its not git-bisect save otherwise.
With this conversion, some parameters are now extracted from the
DT instread of using the config header defines. The supported
properties right now are:
PHY-mode ("phy-mode") and PHY-address ("reg").
The base addresses for the ethernet controllers can be removed from
the header files as well.
Please note that this patch also removes the E1000 network driver
from some MVEBU config headers. This is necessary, as with DM_ETH
configured and the e1000 driver enabled, the PCI driver also needs
to support DM. But the MVEBU PCI(e) driver still needs to get
ported to DM. When this is done, the E1000 driver can be enabled
again.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Simon Glass <sjg@chromium.org>
189 lines
5.1 KiB
C
189 lines
5.1 KiB
C
/*
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* Copyright (C) 2014 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CONFIG_DB_88F6820_GP_H
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#define _CONFIG_DB_88F6820_GP_H
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/*
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* High Level Configuration Options (easy to change)
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*/
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#define CONFIG_ARMADA_XP /* SOC Family Name */
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#define CONFIG_ARMADA_38X
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#define CONFIG_DB_88F6820_GP /* Board target name for DDR training */
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#define CONFIG_SYS_L2_PL310
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
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#endif
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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/*
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* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
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* for DDR ECC byte filling in the SPL before loading the main
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* U-Boot into it.
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*/
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#define CONFIG_SYS_TEXT_BASE 0x00800000
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#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
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/*
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* Commands configuration
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*/
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#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_EXT4
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_FS_GENERIC
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SCSI
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_SPI
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#define CONFIG_CMD_TFTPPUT
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#define CONFIG_CMD_TIME
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MVTWSI
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#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
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#define CONFIG_SYS_I2C_SLAVE 0x0
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#define CONFIG_SYS_I2C_SPEED 100000
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/* SPI NOR flash default params, used by sf commands */
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#define CONFIG_SF_DEFAULT_SPEED 1000000
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
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/*
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* SDIO/MMC Card Configuration
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*/
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#define CONFIG_MMC
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#define CONFIG_MMC_SDMA
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#define CONFIG_GENERIC_MMC
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#define CONFIG_SDHCI
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#define CONFIG_MV_SDHCI
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#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
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/*
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* SATA/SCSI/AHCI configuration
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*/
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#define CONFIG_LIBATA
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#define CONFIG_SCSI_AHCI
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#define CONFIG_SCSI_AHCI_PLAT
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#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
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#define CONFIG_SYS_SCSI_MAX_LUN 1
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#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
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CONFIG_SYS_SCSI_MAX_LUN)
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/* Partition support */
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#define CONFIG_DOS_PARTITION
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#define CONFIG_EFI_PARTITION
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/* Additional FS support/configuration */
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#define CONFIG_SUPPORT_VFAT
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/* USB/EHCI configuration */
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#define CONFIG_EHCI_IS_TDI
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/* Environment in SPI NOR flash */
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
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#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
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#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
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#define CONFIG_PHY_MARVELL /* there is a marvell phy */
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#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
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/* PCIe support */
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_PCI
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#define CONFIG_PCI_MVEBU
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#define CONFIG_PCI_PNP
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#define CONFIG_PCI_SCAN_SHOW
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#endif
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#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
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#define CONFIG_SYS_ALT_MEMTEST
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/* Keep device tree and initrd in lower memory so the kernel can access them */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_high=0x10000000\0" \
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"initrd_high=0x10000000\0"
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/* SPL */
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/*
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* Select the boot device here
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*
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* Currently supported are:
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* SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
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* SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
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*/
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#define SPL_BOOT_SPI_NOR_FLASH 1
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#define SPL_BOOT_SDIO_MMC_CARD 2
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#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
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/* Defines for SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_SIZE (140 << 10)
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#define CONFIG_SPL_TEXT_BASE 0x40000030
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#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
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#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
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#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MALLOC_SIMPLE
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#endif
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
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/* SPL related SPI defines */
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_BUS 0
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#define CONFIG_SPL_SPI_CS 0
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
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#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
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#endif
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#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
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/* SPL related MMC defines */
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SPL_LIBDISK_SUPPORT
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
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#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
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#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512)
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#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB */
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
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#endif
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#endif
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/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
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#define CONFIG_SYS_MVEBU_DDR_A38X
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#define CONFIG_DDR3
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/*
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* mv-common.h should be defined after CMD configs since it used them
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* to enable certain macros
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*/
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#include "mv-common.h"
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#endif /* _CONFIG_DB_88F6820_GP_H */
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