mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
6d0e34bf4e
The sdhci controller assumes that the base clock frequency is fully supported by the peripheral and doesn't support hardware limitations. The Linux kernel distinguishes between base clock (max_clk) of the host controller and maximum frequency (f_max) of the card interface. Use the same differentiation and allow the platform to constrain the peripheral interface. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
134 lines
3.1 KiB
C
134 lines
3.1 KiB
C
/*
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* Copyright 2013 Broadcom Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <sdhci.h>
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#include <linux/errno.h>
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#include <asm/kona-common/clk.h>
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#define SDHCI_CORECTRL_OFFSET 0x00008000
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#define SDHCI_CORECTRL_EN 0x01
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#define SDHCI_CORECTRL_RESET 0x02
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#define SDHCI_CORESTAT_OFFSET 0x00008004
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#define SDHCI_CORESTAT_CD_SW 0x01
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#define SDHCI_COREIMR_OFFSET 0x00008008
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#define SDHCI_COREIMR_IP 0x01
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static int init_kona_mmc_core(struct sdhci_host *host)
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{
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unsigned int mask;
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unsigned int timeout;
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if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL) {
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printf("%s: sd host controller reset error\n", __func__);
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return -EBUSY;
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}
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/* For kona a hardware reset before anything else. */
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mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET) | SDHCI_CORECTRL_RESET;
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sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET);
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/* Wait max 100 ms */
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timeout = 1000;
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do {
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if (timeout == 0) {
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printf("%s: reset timeout error\n", __func__);
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return -ETIMEDOUT;
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}
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timeout--;
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udelay(100);
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} while (0 ==
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(sdhci_readl(host, SDHCI_CORECTRL_OFFSET) &
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SDHCI_CORECTRL_RESET));
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/* Clear the reset bit. */
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mask = mask & ~SDHCI_CORECTRL_RESET;
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sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET);
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/* Enable AHB clock */
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mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET);
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sdhci_writel(host, mask | SDHCI_CORECTRL_EN, SDHCI_CORECTRL_OFFSET);
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/* Enable interrupts */
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sdhci_writel(host, SDHCI_COREIMR_IP, SDHCI_COREIMR_OFFSET);
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/* Make sure Card is detected in controller */
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mask = sdhci_readl(host, SDHCI_CORESTAT_OFFSET);
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sdhci_writel(host, mask | SDHCI_CORESTAT_CD_SW, SDHCI_CORESTAT_OFFSET);
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/* Wait max 100 ms */
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timeout = 1000;
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while (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
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if (timeout == 0) {
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printf("%s: CARD DETECT timeout error\n", __func__);
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return -ETIMEDOUT;
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}
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timeout--;
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udelay(100);
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}
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return 0;
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}
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int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks)
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{
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int ret = 0;
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u32 max_clk;
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void *reg_base;
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struct sdhci_host *host = NULL;
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host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
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if (!host) {
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printf("%s: sdhci host malloc fail!\n", __func__);
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return -ENOMEM;
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}
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switch (dev_index) {
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case 0:
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reg_base = (void *)CONFIG_SYS_SDIO_BASE0;
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ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO0_MAX_CLK,
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&max_clk);
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break;
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case 1:
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reg_base = (void *)CONFIG_SYS_SDIO_BASE1;
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ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO1_MAX_CLK,
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&max_clk);
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break;
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case 2:
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reg_base = (void *)CONFIG_SYS_SDIO_BASE2;
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ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO2_MAX_CLK,
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&max_clk);
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break;
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case 3:
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reg_base = (void *)CONFIG_SYS_SDIO_BASE3;
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ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO3_MAX_CLK,
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&max_clk);
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break;
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default:
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printf("%s: sdio dev index %d not supported\n",
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__func__, dev_index);
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ret = -EINVAL;
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}
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if (ret) {
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free(host);
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return ret;
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}
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host->name = "kona-sdhci";
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host->ioaddr = reg_base;
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host->quirks = quirks;
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host->max_clk = max_clk;
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if (init_kona_mmc_core(host)) {
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free(host);
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return -EINVAL;
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}
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add_sdhci(host, 0, min_clk);
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return ret;
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}
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