mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
53 lines
1.2 KiB
C
53 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*/
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#ifndef _ASM_CACHE_H
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#define _ASM_CACHE_H
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#include <asm/system.h>
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#ifndef CONFIG_ARM64
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/*
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* Invalidate L2 Cache using co-proc instruction
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*/
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#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
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void invalidate_l2_cache(void);
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#else
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static inline void invalidate_l2_cache(void)
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{
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unsigned int val=0;
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asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
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: : "r" (val) : "cc");
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isb();
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}
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#endif
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int check_cache_range(unsigned long start, unsigned long stop);
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void l2_cache_enable(void);
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void l2_cache_disable(void);
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void set_section_dcache(int section, enum dcache_option option);
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void arm_init_before_mmu(void);
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void arm_init_domains(void);
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void cpu_cache_initialization(void);
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void dram_bank_mmu_setup(int bank);
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#endif
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/*
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* The value of the largest data cache relevant to DMA operations shall be set
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* for us in CONFIG_SYS_CACHELINE_SIZE. In some cases this may be a larger
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* value than found in the L1 cache but this is OK to use in terms of
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* alignment.
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*/
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#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
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#endif /* _ASM_CACHE_H */
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