mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
275 lines
8.1 KiB
C
275 lines
8.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2013-2014 Freescale Semiconductor, Inc.
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*/
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#ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__
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#define __ARCH_ARM_MACH_VF610_CCM_REGS_H__
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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/* Clock Controller Module (CCM) */
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struct ccm_reg {
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u32 ccr;
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u32 csr;
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u32 ccsr;
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u32 cacrr;
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u32 cscmr1;
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u32 cscdr1;
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u32 cscdr2;
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u32 cscdr3;
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u32 cscmr2;
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u32 cscdr4;
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u32 ctor;
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u32 clpcr;
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u32 cisr;
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u32 cimr;
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u32 ccosr;
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u32 cgpr;
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u32 ccgr0;
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u32 ccgr1;
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u32 ccgr2;
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u32 ccgr3;
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u32 ccgr4;
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u32 ccgr5;
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u32 ccgr6;
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u32 ccgr7;
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u32 ccgr8;
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u32 ccgr9;
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u32 ccgr10;
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u32 ccgr11;
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u32 cmeor0;
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u32 cmeor1;
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u32 cmeor2;
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u32 cmeor3;
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u32 cmeor4;
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u32 cmeor5;
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u32 cppdsr;
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u32 ccowr;
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u32 ccpgr0;
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u32 ccpgr1;
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u32 ccpgr2;
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u32 ccpgr3;
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};
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/* Analog components control digital interface (ANADIG) */
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struct anadig_reg {
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u32 reserved_0x000[4];
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u32 pll3_ctrl;
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u32 reserved_0x014[3];
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u32 pll7_ctrl;
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u32 reserved_0x024[3];
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u32 pll2_ctrl;
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u32 reserved_0x034[3];
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u32 pll2_ss;
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u32 reserved_0x044[3];
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u32 pll2_num;
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u32 reserved_0x054[3];
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u32 pll2_denom;
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u32 reserved_0x064[3];
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u32 pll4_ctrl;
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u32 reserved_0x074[3];
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u32 pll4_num;
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u32 reserved_0x084[3];
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u32 pll4_denom;
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u32 reserved_0x094[3];
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u32 pll6_ctrl;
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u32 reserved_0x0A4[3];
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u32 pll6_num;
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u32 reserved_0x0B4[3];
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u32 pll6_denom;
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u32 reserved_0x0C4[7];
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u32 pll5_ctrl;
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u32 reserved_0x0E4[3];
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u32 pll3_pfd;
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u32 reserved_0x0F4[3];
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u32 pll2_pfd;
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u32 reserved_0x104[3];
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u32 reg_1p1;
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u32 reserved_0x114[3];
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u32 reg_3p0;
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u32 reserved_0x124[3];
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u32 reg_2p5;
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u32 reserved_0x134[7];
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u32 ana_misc0;
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u32 reserved_0x154[3];
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u32 ana_misc1;
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u32 reserved_0x164[63];
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u32 anadig_digprog;
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u32 reserved_0x264[3];
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u32 pll1_ctrl;
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u32 reserved_0x274[3];
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u32 pll1_ss;
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u32 reserved_0x284[3];
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u32 pll1_num;
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u32 reserved_0x294[3];
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u32 pll1_denom;
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u32 reserved_0x2A4[3];
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u32 pll1_pdf;
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u32 reserved_0x2B4[3];
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u32 pll_lock;
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};
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#endif
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#define CCM_CCR_FIRC_EN (1 << 16)
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#define CCM_CCR_OSCNT_MASK 0xff
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#define CCM_CCR_OSCNT(v) ((v) & 0xff)
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#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19
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#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19)
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#define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19)
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#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16
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#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16)
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#define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16)
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#define CCM_CCSR_PLL2_PFD4_EN (1 << 15)
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#define CCM_CCSR_PLL2_PFD3_EN (1 << 14)
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#define CCM_CCSR_PLL2_PFD2_EN (1 << 13)
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#define CCM_CCSR_PLL2_PFD1_EN (1 << 12)
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#define CCM_CCSR_PLL1_PFD4_EN (1 << 11)
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#define CCM_CCSR_PLL1_PFD3_EN (1 << 10)
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#define CCM_CCSR_PLL1_PFD2_EN (1 << 9)
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#define CCM_CCSR_PLL1_PFD1_EN (1 << 8)
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#define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6)
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#define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5)
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#define CCM_CCSR_SYS_CLK_SEL_OFFSET 0
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#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7
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#define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7)
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#define CCM_CACRR_IPG_CLK_DIV_OFFSET 11
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#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11)
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#define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11)
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#define CCM_CACRR_BUS_CLK_DIV_OFFSET 3
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#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3)
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#define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3)
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#define CCM_CACRR_ARM_CLK_DIV_OFFSET 0
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#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
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#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7)
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#define CCM_CSCMR1_DCU1_CLK_SEL (1 << 29)
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#define CCM_CSCMR1_DCU0_CLK_SEL (1 << 28)
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#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET 22
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#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22)
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#define CCM_CSCMR1_QSPI0_CLK_SEL(v) (((v) & 0x3) << 22)
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#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18
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#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18)
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#define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18)
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#define CCM_CSCMR1_NFC_CLK_SEL_OFFSET 12
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#define CCM_CSCMR1_NFC_CLK_SEL_MASK (0x3 << 12)
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#define CCM_CSCMR1_NFC_CLK_SEL(v) (((v) & 0x3) << 12)
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#define CCM_CSCDR1_RMII_CLK_EN (1 << 24)
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#define CCM_CSCDR2_NFC_EN (1 << 9)
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#define CCM_CSCDR2_NFC_FRAC_DIV_EN (1 << 13)
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#define CCM_CSCDR2_NFC_CLK_INV (1 << 14)
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#define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET 4
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#define CCM_CSCDR2_NFC_FRAC_DIV_MASK (0xf << 4)
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#define CCM_CSCDR2_NFC_FRAC_DIV(v) (((v) & 0xf) << 4)
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#define CCM_CSCDR2_ESDHC1_EN (1 << 29)
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#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20
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#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
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#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20)
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#define CCM_CSCDR3_DCU1_EN (1 << 23)
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#define CCM_CSCDR3_DCU1_DIV_MASK (0x7 << 20)
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#define CCM_CSCDR3_DCU1_DIV(v) (((v) & 0x7) << 20)
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#define CCM_CSCDR3_DCU0_EN (1 << 19)
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#define CCM_CSCDR3_DCU0_DIV_MASK (0x7 << 16)
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#define CCM_CSCDR3_DCU0_DIV(v) (((v) & 0x7) << 16)
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#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET 13
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#define CCM_CSCDR3_NFC_PRE_DIV_MASK (0x7 << 13)
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#define CCM_CSCDR3_NFC_PRE_DIV(v) (((v) & 0x7) << 13)
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#define CCM_CSCDR3_QSPI0_EN (1 << 4)
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#define CCM_CSCDR3_QSPI0_DIV(v) ((v) << 3)
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#define CCM_CSCDR3_QSPI0_X2_DIV(v) ((v) << 2)
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#define CCM_CSCDR3_QSPI0_X4_DIV(v) ((v) & 0x3)
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#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4
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#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4)
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#define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4)
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#define CCM_REG_CTRL_MASK 0xffffffff
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#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14)
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#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
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#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24)
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#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26)
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#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8)
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#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
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#define CCM_CCGR1_TCON0_CTRL_MASK (0x3 << 26)
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#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
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#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8)
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#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16)
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#define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18)
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#define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20)
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#define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22)
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#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24)
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#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26)
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#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
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#define CCM_CCGR3_SCSC_CTRL_MASK (0x3 << 4)
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#define CCM_CCGR3_DCU0_CTRL_MASK (0x3 << 16)
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#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20)
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#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22)
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#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
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#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12)
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#define CCM_CCGR4_I2C1_CTRL_MASK (0x3 << 14)
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#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
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#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24)
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#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26)
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#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)
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#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)
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#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8)
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#define CCM_CCGR9_FEC0_CTRL_MASK 0x3
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#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2)
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#define CCM_CCGR10_NFC_CTRL_MASK 0x3
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#define CCM_CCGR10_I2C2_CTRL_MASK (0x3 << 12)
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#define CCM_CCGR10_I2C3_CTRL_MASK (0x3 << 14)
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#define ANADIG_PLL7_CTRL_BYPASS (1 << 16)
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#define ANADIG_PLL7_CTRL_ENABLE (1 << 13)
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#define ANADIG_PLL7_CTRL_POWERDOWN (1 << 12)
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#define ANADIG_PLL7_CTRL_DIV_SELECT (1 << 1)
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#define ANADIG_PLL5_CTRL_BYPASS (1 << 16)
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#define ANADIG_PLL5_CTRL_ENABLE (1 << 13)
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#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12)
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#define ANADIG_PLL5_CTRL_DIV_SELECT 1
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#define ANADIG_PLL3_CTRL_BYPASS (1 << 16)
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#define ANADIG_PLL3_CTRL_ENABLE (1 << 13)
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#define ANADIG_PLL3_CTRL_POWERDOWN (1 << 12)
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#define ANADIG_PLL3_CTRL_DIV_SELECT (1 << 1)
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#define ANADIG_PLL2_CTRL_ENABLE (1 << 13)
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#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12)
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#define ANADIG_PLL2_CTRL_DIV_SELECT 1
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#define ANADIG_PLL1_CTRL_ENABLE (1 << 13)
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#define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12)
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#define ANADIG_PLL1_CTRL_DIV_SELECT 1
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#define FASE_CLK_FREQ 24000000
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#define SLOW_CLK_FREQ 32000
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#define PLL1_PFD1_FREQ 500000000
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#define PLL1_PFD2_FREQ 452000000
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#define PLL1_PFD3_FREQ 396000000
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#define PLL1_PFD4_FREQ 528000000
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#define PLL1_MAIN_FREQ 528000000
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#define PLL2_PFD1_FREQ 500000000
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#define PLL2_PFD2_FREQ 396000000
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#define PLL2_PFD3_FREQ 339000000
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#define PLL2_PFD4_FREQ 413000000
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#define PLL2_MAIN_FREQ 528000000
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#define PLL3_MAIN_FREQ 480000000
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#define PLL3_PFD3_FREQ 298000000
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#define PLL5_MAIN_FREQ 500000000
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#define ENET_EXTERNAL_CLK 50000000
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#define AUDIO_EXTERNAL_CLK 24576000
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#endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */
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