mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 14:16:17 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
136 lines
2.7 KiB
C
136 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
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*/
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#ifndef _ASM_ARCH_GRF_RK3368_H
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#define _ASM_ARCH_GRF_RK3368_H
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#include <common.h>
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struct rk3368_grf {
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u32 gpio1a_iomux;
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u32 gpio1b_iomux;
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u32 gpio1c_iomux;
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u32 gpio1d_iomux;
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u32 gpio2a_iomux;
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u32 gpio2b_iomux;
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u32 gpio2c_iomux;
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u32 gpio2d_iomux;
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u32 gpio3a_iomux;
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u32 gpio3b_iomux;
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u32 gpio3c_iomux;
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u32 gpio3d_iomux;
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u32 reserved[0x34];
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u32 gpio1a_pull;
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u32 gpio1b_pull;
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u32 gpio1c_pull;
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u32 gpio1d_pull;
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u32 gpio2a_pull;
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u32 gpio2b_pull;
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u32 gpio2c_pull;
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u32 gpio2d_pull;
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u32 gpio3a_pull;
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u32 gpio3b_pull;
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u32 gpio3c_pull;
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u32 gpio3d_pull;
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u32 reserved1[0x34];
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u32 gpio1a_drv;
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u32 gpio1b_drv;
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u32 gpio1c_drv;
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u32 gpio1d_drv;
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u32 gpio2a_drv;
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u32 gpio2b_drv;
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u32 gpio2c_drv;
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u32 gpio2d_drv;
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u32 gpio3a_drv;
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u32 gpio3b_drv;
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u32 gpio3c_drv;
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u32 gpio3d_drv;
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u32 reserved2[0x34];
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u32 gpio1l_sr;
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u32 gpio1h_sr;
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u32 gpio2l_sr;
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u32 gpio2h_sr;
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u32 gpio3l_sr;
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u32 gpio3h_sr;
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u32 reserved3[0x1a];
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u32 gpio_smt;
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u32 reserved4[0x1f];
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u32 soc_con0;
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u32 soc_con1;
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u32 soc_con2;
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u32 soc_con3;
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u32 soc_con4;
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u32 soc_con5;
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u32 soc_con6;
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u32 soc_con7;
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u32 soc_con8;
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u32 soc_con9;
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u32 soc_con10;
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u32 soc_con11;
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u32 soc_con12;
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u32 soc_con13;
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u32 soc_con14;
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u32 soc_con15;
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u32 soc_con16;
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u32 soc_con17;
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u32 reserved5[0x6e];
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u32 ddrc0_con0;
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};
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check_member(rk3368_grf, soc_con17, 0x444);
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check_member(rk3368_grf, ddrc0_con0, 0x600);
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struct rk3368_pmu_grf {
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u32 gpio0a_iomux;
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u32 gpio0b_iomux;
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u32 gpio0c_iomux;
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u32 gpio0d_iomux;
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u32 gpio0a_pull;
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u32 gpio0b_pull;
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u32 gpio0c_pull;
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u32 gpio0d_pull;
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u32 gpio0a_drv;
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u32 gpio0b_drv;
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u32 gpio0c_drv;
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u32 gpio0d_drv;
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u32 gpio0l_sr;
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u32 gpio0h_sr;
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u32 reserved[0x72];
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u32 os_reg[4];
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};
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check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
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check_member(rk3368_pmu_grf, os_reg[0], 0x200);
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/*GRF_SOC_CON11/12/13*/
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enum {
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MCU_SRAM_BASE_BIT27_BIT12_SHIFT = 0,
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MCU_SRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
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};
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/*GRF_SOC_CON12*/
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enum {
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MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT = 0,
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MCU_EXSRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
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};
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/*GRF_SOC_CON13*/
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enum {
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MCU_EXPERI_BASE_BIT27_BIT12_SHIFT = 0,
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MCU_EXPERI_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
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};
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/*GRF_SOC_CON14*/
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enum {
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MCU_EXPERI_BASE_BIT31_BIT28_SHIFT = 12,
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MCU_EXPERI_BASE_BIT31_BIT28_MASK = GENMASK(15, 12),
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MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT = 8,
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MCU_EXSRAM_BASE_BIT31_BIT28_MASK = GENMASK(11, 8),
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MCU_SRAM_BASE_BIT31_BIT28_SHIFT = 4,
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MCU_SRAM_BASE_BIT31_BIT28_MASK = GENMASK(7, 4),
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MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0,
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MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0),
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};
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#endif
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