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https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
147 lines
5.5 KiB
C
147 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Freescale i.MX28 DIGCTL Register Definitions
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*
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* Copyright (C) 2012 Robert Delien <robert@delien.nl>
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*/
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#ifndef __MX28_REGS_DIGCTL_H__
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#define __MX28_REGS_DIGCTL_H__
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#include <asm/mach-imx/regs-common.h>
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#ifndef __ASSEMBLY__
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struct mxs_digctl_regs {
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mxs_reg_32(hw_digctl_ctrl) /* 0x000 */
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mxs_reg_32(hw_digctl_status) /* 0x010 */
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mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */
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mxs_reg_32(hw_digctl_ramctrl) /* 0x030 */
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mxs_reg_32(hw_digctl_emi_status) /* 0x040 */
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mxs_reg_32(hw_digctl_read_margin) /* 0x050 */
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uint32_t hw_digctl_writeonce; /* 0x060 */
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uint32_t reserved_writeonce[3];
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mxs_reg_32(hw_digctl_bist_ctl) /* 0x070 */
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mxs_reg_32(hw_digctl_bist_status) /* 0x080 */
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uint32_t hw_digctl_entropy; /* 0x090 */
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uint32_t reserved_entropy[3];
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uint32_t hw_digctl_entropy_latched; /* 0x0a0 */
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uint32_t reserved_entropy_latched[3];
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uint32_t reserved1[4];
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mxs_reg_32(hw_digctl_microseconds) /* 0x0c0 */
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uint32_t hw_digctl_dbgrd; /* 0x0d0 */
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uint32_t reserved_hw_digctl_dbgrd[3];
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uint32_t hw_digctl_dbg; /* 0x0e0 */
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uint32_t reserved_hw_digctl_dbg[3];
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uint32_t reserved2[4];
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mxs_reg_32(hw_digctl_usb_loopback) /* 0x100 */
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mxs_reg_32(hw_digctl_ocram_status0) /* 0x110 */
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mxs_reg_32(hw_digctl_ocram_status1) /* 0x120 */
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mxs_reg_32(hw_digctl_ocram_status2) /* 0x130 */
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mxs_reg_32(hw_digctl_ocram_status3) /* 0x140 */
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mxs_reg_32(hw_digctl_ocram_status4) /* 0x150 */
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mxs_reg_32(hw_digctl_ocram_status5) /* 0x160 */
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mxs_reg_32(hw_digctl_ocram_status6) /* 0x170 */
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mxs_reg_32(hw_digctl_ocram_status7) /* 0x180 */
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mxs_reg_32(hw_digctl_ocram_status8) /* 0x190 */
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mxs_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */
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mxs_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */
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mxs_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */
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mxs_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */
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mxs_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */
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uint32_t reserved3[36];
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uint32_t hw_digctl_scratch0; /* 0x280 */
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uint32_t reserved_hw_digctl_scratch0[3];
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uint32_t hw_digctl_scratch1; /* 0x290 */
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uint32_t reserved_hw_digctl_scratch1[3];
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uint32_t hw_digctl_armcache; /* 0x2a0 */
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uint32_t reserved_hw_digctl_armcache[3];
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mxs_reg_32(hw_digctl_debug_trap) /* 0x2b0 */
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uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */
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uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3];
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uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */
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uint32_t reserved_hw_digctl_debug_trap_l0_addr_high[3];
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uint32_t hw_digctl_debug_trap_l3_addr_low; /* 0x2e0 */
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uint32_t reserved_hw_digctl_debug_trap_l3_addr_low[3];
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uint32_t hw_digctl_debug_trap_l3_addr_high; /* 0x2f0 */
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uint32_t reserved_hw_digctl_debug_trap_l3_addr_high[3];
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uint32_t hw_digctl_fsl; /* 0x300 */
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uint32_t reserved_hw_digctl_fsl[3];
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uint32_t hw_digctl_chipid; /* 0x310 */
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uint32_t reserved_hw_digctl_chipid[3];
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uint32_t reserved4[4];
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uint32_t hw_digctl_ahb_stats_select; /* 0x330 */
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uint32_t reserved_hw_digctl_ahb_stats_select[3];
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uint32_t reserved5[12];
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uint32_t hw_digctl_l1_ahb_active_cycles; /* 0x370 */
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uint32_t reserved_hw_digctl_l1_ahb_active_cycles[3];
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uint32_t hw_digctl_l1_ahb_data_stalled; /* 0x380 */
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uint32_t reserved_hw_digctl_l1_ahb_data_stalled[3];
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uint32_t hw_digctl_l1_ahb_data_cycles; /* 0x390 */
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uint32_t reserved_hw_digctl_l1_ahb_data_cycles[3];
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uint32_t hw_digctl_l2_ahb_active_cycles; /* 0x3a0 */
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uint32_t reserved_hw_digctl_l2_ahb_active_cycles[3];
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uint32_t hw_digctl_l2_ahb_data_stalled; /* 0x3b0 */
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uint32_t reserved_hw_digctl_l2_ahb_data_stalled[3];
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uint32_t hw_digctl_l2_ahb_data_cycles; /* 0x3c0 */
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uint32_t reserved_hw_digctl_l2_ahb_data_cycles[3];
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uint32_t hw_digctl_l3_ahb_active_cycles; /* 0x3d0 */
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uint32_t reserved_hw_digctl_l3_ahb_active_cycles[3];
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uint32_t hw_digctl_l3_ahb_data_stalled; /* 0x3e0 */
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uint32_t reserved_hw_digctl_l3_ahb_data_stalled[3];
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uint32_t hw_digctl_l3_ahb_data_cycles; /* 0x3f0 */
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uint32_t reserved_hw_digctl_l3_ahb_data_cycles[3];
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uint32_t reserved6[64];
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uint32_t hw_digctl_mpte0_loc; /* 0x500 */
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uint32_t reserved_hw_digctl_mpte0_loc[3];
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uint32_t hw_digctl_mpte1_loc; /* 0x510 */
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uint32_t reserved_hw_digctl_mpte1_loc[3];
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uint32_t hw_digctl_mpte2_loc; /* 0x520 */
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uint32_t reserved_hw_digctl_mpte2_loc[3];
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uint32_t hw_digctl_mpte3_loc; /* 0x530 */
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uint32_t reserved_hw_digctl_mpte3_loc[3];
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uint32_t hw_digctl_mpte4_loc; /* 0x540 */
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uint32_t reserved_hw_digctl_mpte4_loc[3];
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uint32_t hw_digctl_mpte5_loc; /* 0x550 */
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uint32_t reserved_hw_digctl_mpte5_loc[3];
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uint32_t hw_digctl_mpte6_loc; /* 0x560 */
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uint32_t reserved_hw_digctl_mpte6_loc[3];
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uint32_t hw_digctl_mpte7_loc; /* 0x570 */
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uint32_t reserved_hw_digctl_mpte7_loc[3];
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uint32_t hw_digctl_mpte8_loc; /* 0x580 */
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uint32_t reserved_hw_digctl_mpte8_loc[3];
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uint32_t hw_digctl_mpte9_loc; /* 0x590 */
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uint32_t reserved_hw_digctl_mpte9_loc[3];
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uint32_t hw_digctl_mpte10_loc; /* 0x5a0 */
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uint32_t reserved_hw_digctl_mpte10_loc[3];
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uint32_t hw_digctl_mpte11_loc; /* 0x5b0 */
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uint32_t reserved_hw_digctl_mpte11_loc[3];
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uint32_t hw_digctl_mpte12_loc; /* 0x5c0 */
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uint32_t reserved_hw_digctl_mpte12_loc[3];
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uint32_t hw_digctl_mpte13_loc; /* 0x5d0 */
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uint32_t reserved_hw_digctl_mpte13_loc[3];
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uint32_t hw_digctl_mpte14_loc; /* 0x5e0 */
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uint32_t reserved_hw_digctl_mpte14_loc[3];
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uint32_t hw_digctl_mpte15_loc; /* 0x5f0 */
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uint32_t reserved_hw_digctl_mpte15_loc[3];
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};
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#endif
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/* Product code identification */
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#define HW_DIGCTL_CHIPID_MASK (0xffff << 16)
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#define HW_DIGCTL_CHIPID_MX23 (0x3780 << 16)
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#define HW_DIGCTL_CHIPID_MX28 (0x2800 << 16)
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#endif /* __MX28_REGS_DIGCTL_H__ */
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