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https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
283 lines
11 KiB
C
283 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Freescale i.MX28 CLKCTRL Register Definitions
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* Based on code from LTIB:
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* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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#ifndef __MX28_REGS_CLKCTRL_H__
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#define __MX28_REGS_CLKCTRL_H__
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#include <asm/mach-imx/regs-common.h>
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#ifndef __ASSEMBLY__
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struct mxs_clkctrl_regs {
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mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
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uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */
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uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */
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mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */
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uint32_t hw_clkctrl_pll1ctrl1; /* 0x30 */
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uint32_t reserved_pll1ctrl1[3]; /* 0x34-0x3c */
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mxs_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */
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mxs_reg_32(hw_clkctrl_cpu) /* 0x50 */
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mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */
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mxs_reg_32(hw_clkctrl_xbus) /* 0x70 */
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mxs_reg_32(hw_clkctrl_xtal) /* 0x80 */
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mxs_reg_32(hw_clkctrl_ssp0) /* 0x90 */
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mxs_reg_32(hw_clkctrl_ssp1) /* 0xa0 */
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mxs_reg_32(hw_clkctrl_ssp2) /* 0xb0 */
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mxs_reg_32(hw_clkctrl_ssp3) /* 0xc0 */
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mxs_reg_32(hw_clkctrl_gpmi) /* 0xd0 */
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mxs_reg_32(hw_clkctrl_spdif) /* 0xe0 */
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mxs_reg_32(hw_clkctrl_emi) /* 0xf0 */
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mxs_reg_32(hw_clkctrl_saif0) /* 0x100 */
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mxs_reg_32(hw_clkctrl_saif1) /* 0x110 */
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mxs_reg_32(hw_clkctrl_lcdif) /* 0x120 */
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mxs_reg_32(hw_clkctrl_etm) /* 0x130 */
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mxs_reg_32(hw_clkctrl_enet) /* 0x140 */
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mxs_reg_32(hw_clkctrl_hsadc) /* 0x150 */
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mxs_reg_32(hw_clkctrl_flexcan) /* 0x160 */
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uint32_t reserved[16];
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mxs_reg_8(hw_clkctrl_frac0) /* 0x1b0 */
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mxs_reg_8(hw_clkctrl_frac1) /* 0x1c0 */
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mxs_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */
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mxs_reg_32(hw_clkctrl_reset) /* 0x1e0 */
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mxs_reg_32(hw_clkctrl_status) /* 0x1f0 */
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mxs_reg_32(hw_clkctrl_version) /* 0x200 */
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};
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#endif
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#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28)
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#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28
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#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28)
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#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28)
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#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28)
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#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28)
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#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24)
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#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24
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#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24)
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#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24)
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#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24)
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#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24)
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#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20)
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#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20
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#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20)
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#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20)
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#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20)
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#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20)
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#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18)
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#define CLKCTRL_PLL0CTRL0_POWER (1 << 17)
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#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31)
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#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30)
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#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff
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#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0
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#define CLKCTRL_PLL1CTRL0_CLKGATEEMI (1 << 31)
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#define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK (0x3 << 28)
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#define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET 28
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#define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT (0x0 << 28)
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#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2 (0x1 << 28)
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#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05 (0x2 << 28)
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#define CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED (0x3 << 28)
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#define CLKCTRL_PLL1CTRL0_CP_SEL_MASK (0x3 << 24)
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#define CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET 24
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#define CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT (0x0 << 24)
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#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2 (0x1 << 24)
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#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05 (0x2 << 24)
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#define CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED (0x3 << 24)
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#define CLKCTRL_PLL1CTRL0_DIV_SEL_MASK (0x3 << 20)
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#define CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET 20
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#define CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT (0x0 << 20)
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#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER (0x1 << 20)
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#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST (0x2 << 20)
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#define CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED (0x3 << 20)
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#define CLKCTRL_PLL1CTRL0_EN_USB_CLKS (1 << 18)
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#define CLKCTRL_PLL1CTRL0_POWER (1 << 17)
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#define CLKCTRL_PLL1CTRL1_LOCK (1 << 31)
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#define CLKCTRL_PLL1CTRL1_FORCE_LOCK (1 << 30)
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#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK 0xffff
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#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET 0
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#define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31)
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#define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK (0x3 << 28)
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#define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET 28
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#define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B (1 << 26)
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#define CLKCTRL_PLL2CTRL0_CP_SEL_MASK (0x3 << 24)
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#define CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET 24
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#define CLKCTRL_PLL2CTRL0_POWER (1 << 23)
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#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29)
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#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28)
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#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26)
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#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16)
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#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16
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#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12)
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#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10)
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#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f
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#define CLKCTRL_CPU_DIV_CPU_OFFSET 0
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#define CLKCTRL_HBUS_ASM_BUSY (1 << 31)
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#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 30)
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#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 29)
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#define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE (1 << 27)
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#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26)
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#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25)
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#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24)
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#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23)
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#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22)
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#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21)
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#define CLKCTRL_HBUS_ASM_ENABLE (1 << 20)
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#define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE (1 << 19)
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#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16)
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#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16
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#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16)
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#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16)
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#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16)
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#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16)
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#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16)
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#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16)
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#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5)
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#define CLKCTRL_HBUS_DIV_MASK 0x1f
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#define CLKCTRL_HBUS_DIV_OFFSET 0
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#define CLKCTRL_XBUS_BUSY (1 << 31)
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#define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE (1 << 11)
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#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10)
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#define CLKCTRL_XBUS_DIV_MASK 0x3ff
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#define CLKCTRL_XBUS_DIV_OFFSET 0
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#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31)
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#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29)
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#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26)
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#define CLKCTRL_XTAL_DIV_UART_MASK 0x3
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#define CLKCTRL_XTAL_DIV_UART_OFFSET 0
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#define CLKCTRL_SSP_CLKGATE (1 << 31)
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#define CLKCTRL_SSP_BUSY (1 << 29)
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#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9)
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#define CLKCTRL_SSP_DIV_MASK 0x1ff
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#define CLKCTRL_SSP_DIV_OFFSET 0
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#define CLKCTRL_GPMI_CLKGATE (1 << 31)
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#define CLKCTRL_GPMI_BUSY (1 << 29)
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#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10)
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#define CLKCTRL_GPMI_DIV_MASK 0x3ff
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#define CLKCTRL_GPMI_DIV_OFFSET 0
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#define CLKCTRL_SPDIF_CLKGATE (1 << 31)
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#define CLKCTRL_EMI_CLKGATE (1 << 31)
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#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30)
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#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29)
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#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28)
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#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27)
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#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26)
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#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17)
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#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16)
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#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8)
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#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8
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#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f
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#define CLKCTRL_EMI_DIV_EMI_OFFSET 0
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#define CLKCTRL_SAIF0_CLKGATE (1 << 31)
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#define CLKCTRL_SAIF0_BUSY (1 << 29)
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#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16)
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#define CLKCTRL_SAIF0_DIV_MASK 0xffff
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#define CLKCTRL_SAIF0_DIV_OFFSET 0
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#define CLKCTRL_SAIF1_CLKGATE (1 << 31)
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#define CLKCTRL_SAIF1_BUSY (1 << 29)
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#define CLKCTRL_SAIF1_DIV_FRAC_EN (1 << 16)
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#define CLKCTRL_SAIF1_DIV_MASK 0xffff
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#define CLKCTRL_SAIF1_DIV_OFFSET 0
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#define CLKCTRL_DIS_LCDIF_CLKGATE (1 << 31)
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#define CLKCTRL_DIS_LCDIF_BUSY (1 << 29)
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#define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN (1 << 13)
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#define CLKCTRL_DIS_LCDIF_DIV_MASK 0x1fff
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#define CLKCTRL_DIS_LCDIF_DIV_OFFSET 0
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#define CLKCTRL_ETM_CLKGATE (1 << 31)
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#define CLKCTRL_ETM_BUSY (1 << 29)
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#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 7)
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#define CLKCTRL_ETM_DIV_MASK 0x7f
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#define CLKCTRL_ETM_DIV_OFFSET 0
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#define CLKCTRL_ENET_SLEEP (1 << 31)
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#define CLKCTRL_ENET_DISABLE (1 << 30)
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#define CLKCTRL_ENET_STATUS (1 << 29)
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#define CLKCTRL_ENET_BUSY_TIME (1 << 27)
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#define CLKCTRL_ENET_DIV_TIME_MASK (0x3f << 21)
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#define CLKCTRL_ENET_DIV_TIME_OFFSET 21
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#define CLKCTRL_ENET_TIME_SEL_MASK (0x3 << 19)
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#define CLKCTRL_ENET_TIME_SEL_OFFSET 19
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#define CLKCTRL_ENET_TIME_SEL_XTAL (0x0 << 19)
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#define CLKCTRL_ENET_TIME_SEL_PLL (0x1 << 19)
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#define CLKCTRL_ENET_TIME_SEL_RMII_CLK (0x2 << 19)
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#define CLKCTRL_ENET_TIME_SEL_UNDEFINED (0x3 << 19)
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#define CLKCTRL_ENET_CLK_OUT_EN (1 << 18)
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#define CLKCTRL_ENET_RESET_BY_SW_CHIP (1 << 17)
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#define CLKCTRL_ENET_RESET_BY_SW (1 << 16)
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#define CLKCTRL_HSADC_RESETB (1 << 30)
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#define CLKCTRL_HSADC_FREQDIV_MASK (0x3 << 28)
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#define CLKCTRL_HSADC_FREQDIV_OFFSET 28
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#define CLKCTRL_FLEXCAN_STOP_CAN0 (1 << 30)
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#define CLKCTRL_FLEXCAN_CAN0_STATUS (1 << 29)
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#define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28)
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#define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27)
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#define CLKCTRL_FRAC_CLKGATE (1 << 7)
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#define CLKCTRL_FRAC_STABLE (1 << 6)
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#define CLKCTRL_FRAC_FRAC_MASK 0x3f
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#define CLKCTRL_FRAC_FRAC_OFFSET 0
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#define CLKCTRL_FRAC0_CPU 0
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#define CLKCTRL_FRAC0_EMI 1
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#define CLKCTRL_FRAC0_IO1 2
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#define CLKCTRL_FRAC0_IO0 3
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#define CLKCTRL_FRAC1_PIX 0
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#define CLKCTRL_FRAC1_HSADC 1
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#define CLKCTRL_FRAC1_GPMI 2
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#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18)
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#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14)
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#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS (0x1 << 14)
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#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD (0x0 << 14)
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#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8)
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#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7)
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#define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6)
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#define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5)
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#define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4)
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#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3)
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#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2)
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#define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1)
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#define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0)
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#define CLKCTRL_RESET_WDOG_POR_DISABLE (1 << 5)
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#define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE (1 << 4)
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#define CLKCTRL_RESET_THERMAL_RESET_ENABLE (1 << 3)
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#define CLKCTRL_RESET_THERMAL_RESET_DEFAULT (1 << 2)
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#define CLKCTRL_RESET_CHIP (1 << 1)
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#define CLKCTRL_RESET_DIG (1 << 0)
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#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30)
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#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30
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#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24)
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#define CLKCTRL_VERSION_MAJOR_OFFSET 24
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#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16)
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#define CLKCTRL_VERSION_MINOR_OFFSET 16
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#define CLKCTRL_VERSION_STEP_MASK 0xffff
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#define CLKCTRL_VERSION_STEP_OFFSET 0
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#endif /* __MX28_REGS_CLKCTRL_H__ */
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