mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 06:06:15 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
126 lines
3.5 KiB
ArmAsm
126 lines
3.5 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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*
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* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
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*/
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#include <asm/arch/imx-regs.h>
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#include <generated/asm-offsets.h>
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#include <asm/macro.h>
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/*
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* AIPS setup - Only setup MPROTx registers.
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* The PACR default values are good.
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*
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* Default argument values:
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* - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
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* user-mode.
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* - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for
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* SDMA to access them.
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*/
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.macro init_aips mpr=0x77777777, opacr=0x00000000
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ldr r0, =AIPS1_BASE_ADDR
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ldr r1, =\mpr
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str r1, [r0, #AIPS_MPR_0_7]
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str r1, [r0, #AIPS_MPR_8_15]
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ldr r2, =AIPS2_BASE_ADDR
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str r1, [r2, #AIPS_MPR_0_7]
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str r1, [r2, #AIPS_MPR_8_15]
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/* Did not change the AIPS control registers access type. */
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ldr r1, =\opacr
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str r1, [r0, #AIPS_OPACR_0_7]
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str r1, [r0, #AIPS_OPACR_8_15]
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str r1, [r0, #AIPS_OPACR_16_23]
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str r1, [r0, #AIPS_OPACR_24_31]
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str r1, [r0, #AIPS_OPACR_32_39]
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str r1, [r2, #AIPS_OPACR_0_7]
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str r1, [r2, #AIPS_OPACR_8_15]
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str r1, [r2, #AIPS_OPACR_16_23]
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str r1, [r2, #AIPS_OPACR_24_31]
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str r1, [r2, #AIPS_OPACR_32_39]
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.endm
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/*
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* MAX (Multi-Layer AHB Crossbar Switch) setup
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*
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* Default argument values:
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* - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1
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* - SGPCR: always park on last master
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* - MGPCR: restore default values
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*/
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.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000
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ldr r0, =MAX_BASE_ADDR
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ldr r1, =\mpr
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str r1, [r0, #MAX_MPR0] /* for S0 */
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str r1, [r0, #MAX_MPR1] /* for S1 */
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str r1, [r0, #MAX_MPR2] /* for S2 */
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str r1, [r0, #MAX_MPR3] /* for S3 */
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str r1, [r0, #MAX_MPR4] /* for S4 */
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ldr r1, =\sgpcr
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str r1, [r0, #MAX_SGPCR0] /* for S0 */
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str r1, [r0, #MAX_SGPCR1] /* for S1 */
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str r1, [r0, #MAX_SGPCR2] /* for S2 */
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str r1, [r0, #MAX_SGPCR3] /* for S3 */
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str r1, [r0, #MAX_SGPCR4] /* for S4 */
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ldr r1, =\mgpcr
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str r1, [r0, #MAX_MGPCR0] /* for M0 */
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str r1, [r0, #MAX_MGPCR1] /* for M1 */
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str r1, [r0, #MAX_MGPCR2] /* for M2 */
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str r1, [r0, #MAX_MGPCR3] /* for M3 */
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str r1, [r0, #MAX_MGPCR4] /* for M4 */
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str r1, [r0, #MAX_MGPCR5] /* for M5 */
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.endm
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/*
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* M3IF setup
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*
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* Default argument values:
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* - CTL:
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* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
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* MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000
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* MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000
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* MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000
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* MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
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* MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000
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* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
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* MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000
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* ------------
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* 0x00000040
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*/
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.macro init_m3if ctl=0x00000040
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/* M3IF Control Register (M3IFCTL) */
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write32 M3IF_BASE_ADDR, \ctl
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.endm
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.macro core_init
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mrc p15, 0, r1, c1, c0, 0
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/* Set branch prediction enable */
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mrc p15, 0, r0, c1, c0, 1
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orr r0, r0, #7
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mcr p15, 0, r0, c1, c0, 1
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orr r1, r1, #1 << 11
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/* Set unaligned access enable */
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orr r1, r1, #1 << 22
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/* Set low int latency enable */
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orr r1, r1, #1 << 21
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mcr p15, 0, r1, c1, c0, 0
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mov r0, #0
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mcr p15, 0, r0, c15, c2, 4
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mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */
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mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */
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mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */
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/* Setup the Peripheral Port Memory Remap Register */
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ldr r0, =0x40000015 /* Start from AIPS 2-GB region */
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mcr p15, 0, r0, c15, c2, 4
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.endm
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