mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 06:06:15 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
89 lines
2.5 KiB
C
89 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2016 Carlo Caione <carlo@caione.org>
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*/
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#ifndef __SD_EMMC_H__
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#define __SD_EMMC_H__
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#include <mmc.h>
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#define SDIO_PORT_A 0
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#define SDIO_PORT_B 1
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#define SDIO_PORT_C 2
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#define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */
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#define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */
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#define MESON_SD_EMMC_CLOCK 0x00
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#define CLK_MAX_DIV 63
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#define CLK_SRC_24M (0 << 6)
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#define CLK_SRC_DIV2 (1 << 6)
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#define CLK_CO_PHASE_000 (0 << 8)
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#define CLK_CO_PHASE_090 (1 << 8)
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#define CLK_CO_PHASE_180 (2 << 8)
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#define CLK_CO_PHASE_270 (3 << 8)
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#define CLK_TX_PHASE_000 (0 << 10)
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#define CLK_TX_PHASE_090 (1 << 10)
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#define CLK_TX_PHASE_180 (2 << 10)
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#define CLK_TX_PHASE_270 (3 << 10)
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#define CLK_ALWAYS_ON BIT(24)
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#define MESON_SD_EMMC_CFG 0x44
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#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
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#define CFG_BUS_WIDTH_1 0
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#define CFG_BUS_WIDTH_4 1
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#define CFG_BUS_WIDTH_8 2
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#define CFG_BL_LEN_MASK GENMASK(7, 4)
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#define CFG_BL_LEN_SHIFT 4
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#define CFG_BL_LEN_512 (9 << 4)
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#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
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#define CFG_RESP_TIMEOUT_256 (8 << 8)
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#define CFG_RC_CC_MASK GENMASK(15, 12)
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#define CFG_RC_CC_16 (4 << 12)
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#define CFG_SDCLK_ALWAYS_ON BIT(18)
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#define CFG_AUTO_CLK BIT(23)
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#define MESON_SD_EMMC_STATUS 0x48
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#define STATUS_MASK GENMASK(15, 0)
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#define STATUS_ERR_MASK GENMASK(12, 0)
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#define STATUS_RXD_ERR_MASK GENMASK(7, 0)
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#define STATUS_TXD_ERR BIT(8)
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#define STATUS_DESC_ERR BIT(9)
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#define STATUS_RESP_ERR BIT(10)
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#define STATUS_RESP_TIMEOUT BIT(11)
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#define STATUS_DESC_TIMEOUT BIT(12)
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#define STATUS_END_OF_CHAIN BIT(13)
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#define MESON_SD_EMMC_IRQ_EN 0x4c
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#define MESON_SD_EMMC_CMD_CFG 0x50
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#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
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#define CMD_CFG_BLOCK_MODE BIT(9)
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#define CMD_CFG_R1B BIT(10)
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#define CMD_CFG_END_OF_CHAIN BIT(11)
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#define CMD_CFG_TIMEOUT_4S (12 << 12)
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#define CMD_CFG_NO_RESP BIT(16)
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#define CMD_CFG_DATA_IO BIT(18)
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#define CMD_CFG_DATA_WR BIT(19)
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#define CMD_CFG_RESP_NOCRC BIT(20)
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#define CMD_CFG_RESP_128 BIT(21)
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#define CMD_CFG_CMD_INDEX_SHIFT 24
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#define CMD_CFG_OWNER BIT(31)
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#define MESON_SD_EMMC_CMD_ARG 0x54
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#define MESON_SD_EMMC_CMD_DAT 0x58
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#define MESON_SD_EMMC_CMD_RSP 0x5c
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#define MESON_SD_EMMC_CMD_RSP1 0x60
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#define MESON_SD_EMMC_CMD_RSP2 0x64
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#define MESON_SD_EMMC_CMD_RSP3 0x68
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struct meson_mmc_platdata {
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struct mmc_config cfg;
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struct mmc mmc;
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void *regbase;
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void *w_buf;
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};
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#endif
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