mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 14:16:17 +09:00
d96a782d09
The Amlogic Meson SoCs ROM supports a boot over USB with a custom protocol. When no other boot medium are available (or by forcing the USB mode), the ROM sets the primary USB port as device mode and waits for a Host to enumerate. When enumerated, a custom protocol described at [1] permits writing to memory and execute some specific FIP init code to run the loaded Arm Trusted Firmware BL2 and BL3 stages before running the BL33 stage. In this mode, we can load different binaries that can be used by U-boot like a script image file. This adds support for a custom USB boot stage only available when the boot mode is USB and the script file at a pre-defined address is valid. This support was heavily copied from the Sunxi Allwinner FEL U-Boot support. The tool pyamlboot described at [2], permits using this boot mode on boards exposing the first USB port, either as OTG or Host port. [1] https://github.com/superna9999/pyamlboot/blob/master/PROTOCOL.md [2] https://github.com/superna9999/pyamlboot/blob/master/README.md Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
61 lines
1.8 KiB
C
61 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
|
|
*/
|
|
|
|
#ifndef __GX_H__
|
|
#define __GX_H__
|
|
|
|
#define GX_FIRMWARE_MEM_SIZE 0x1000000
|
|
|
|
#define GX_AOBUS_BASE 0xc8100000
|
|
#define GX_PERIPHS_BASE 0xc8834400
|
|
#define GX_HIU_BASE 0xc883c000
|
|
#define GX_ETH_BASE 0xc9410000
|
|
|
|
/* Always-On Peripherals registers */
|
|
#define GX_AO_ADDR(off) (GX_AOBUS_BASE + ((off) << 2))
|
|
|
|
#define GX_AO_SEC_GP_CFG0 GX_AO_ADDR(0x90)
|
|
#define GX_AO_SEC_GP_CFG3 GX_AO_ADDR(0x93)
|
|
#define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94)
|
|
#define GX_AO_SEC_GP_CFG5 GX_AO_ADDR(0x95)
|
|
|
|
#define GX_AO_BOOT_DEVICE 0xF
|
|
#define GX_AO_MEM_SIZE_MASK 0xFFFF0000
|
|
#define GX_AO_MEM_SIZE_SHIFT 16
|
|
#define GX_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000
|
|
#define GX_AO_BL31_RSVMEM_SIZE_SHIFT 16
|
|
#define GX_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
|
|
|
|
/* Peripherals registers */
|
|
#define GX_PERIPHS_ADDR(off) (GX_PERIPHS_BASE + ((off) << 2))
|
|
|
|
/* GPIO registers 0 to 6 */
|
|
#define _GX_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n))
|
|
#define GX_GPIO_EN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 0)
|
|
#define GX_GPIO_IN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1)
|
|
#define GX_GPIO_OUT(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2)
|
|
|
|
#define GX_ETH_REG_0 GX_PERIPHS_ADDR(0x50)
|
|
#define GX_ETH_REG_1 GX_PERIPHS_ADDR(0x51)
|
|
#define GX_ETH_REG_2 GX_PERIPHS_ADDR(0x56)
|
|
#define GX_ETH_REG_3 GX_PERIPHS_ADDR(0x57)
|
|
|
|
#define GX_ETH_REG_0_PHY_INTF BIT(0)
|
|
#define GX_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
|
|
#define GX_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
|
|
#define GX_ETH_REG_0_PHY_CLK_EN BIT(10)
|
|
#define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11)
|
|
#define GX_ETH_REG_0_CLK_EN BIT(12)
|
|
|
|
/* HIU registers */
|
|
#define GX_HIU_ADDR(off) (GX_HIU_BASE + ((off) << 2))
|
|
|
|
#define GX_MEM_PD_REG_0 GX_HIU_ADDR(0x40)
|
|
|
|
/* Ethernet memory power domain */
|
|
#define GX_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
|
|
|
|
#endif /* __GX_H__ */
|