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https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
67 lines
2.1 KiB
C
67 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* LPC32xx DMA Controller Interface
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*
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* Copyright (C) 2008 by NXP Semiconductors
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* @Author: Kevin Wells
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* @Descr: Definitions for LPC3250 chip
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* @References: NXP LPC3250 User's Guide
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*/
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#ifndef _LPC32XX_DMA_H
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#define _LPC32XX_DMA_H
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#include <common.h>
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/*
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* DMA linked list structure used with a channel's LLI register;
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* refer to UM10326, "LPC32x0 and LPC32x0/01 User manual" - Rev. 3
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* tables 84, 85, 86 & 87 for details.
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*/
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struct lpc32xx_dmac_ll {
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u32 dma_src;
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u32 dma_dest;
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u32 next_lli;
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u32 next_ctrl;
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};
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/* control register definitions */
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#define DMAC_CHAN_INT_TC_EN (1 << 31) /* channel terminal count interrupt */
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#define DMAC_CHAN_DEST_AUTOINC (1 << 27) /* automatic destination increment */
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#define DMAC_CHAN_SRC_AUTOINC (1 << 26) /* automatic source increment */
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#define DMAC_CHAN_DEST_AHB1 (1 << 25) /* AHB1 master for dest. transfer */
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#define DMAC_CHAN_DEST_WIDTH_32 (1 << 22) /* Destination data width selection */
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#define DMAC_CHAN_SRC_WIDTH_32 (1 << 19) /* Source data width selection */
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#define DMAC_CHAN_DEST_BURST_1 0
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#define DMAC_CHAN_DEST_BURST_4 (1 << 15) /* Destination data burst size */
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#define DMAC_CHAN_SRC_BURST_1 0
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#define DMAC_CHAN_SRC_BURST_4 (1 << 12) /* Source data burst size */
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/*
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* config_ch register definitions
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* DMAC_CHAN_FLOW_D_xxx: flow control with DMA as the controller
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* DMAC_DEST_PERIP: Macro for loading destination peripheral
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* DMAC_SRC_PERIP: Macro for loading source peripheral
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*/
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#define DMAC_CHAN_FLOW_D_M2P (0x1 << 11)
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#define DMAC_CHAN_FLOW_D_P2M (0x2 << 11)
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#define DMAC_DEST_PERIP(n) (((n) & 0x1F) << 6)
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#define DMAC_SRC_PERIP(n) (((n) & 0x1F) << 1)
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/*
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* config_ch register definitions
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* (source and destination peripheral ID numbers).
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* These can be used with the DMAC_DEST_PERIP and DMAC_SRC_PERIP macros.
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*/
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#define DMA_PERID_NAND1 1
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/* Channel enable bit */
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#define DMAC_CHAN_ENABLE (1 << 0)
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int lpc32xx_dma_get_channel(void);
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int lpc32xx_dma_start_xfer(unsigned int channel,
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const struct lpc32xx_dmac_ll *desc, u32 config);
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int lpc32xx_dma_wait_status(unsigned int channel);
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#endif /* _LPC32XX_DMA_H */
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