mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 06:06:15 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
54 lines
2.4 KiB
C
54 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
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*/
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#ifndef _LPC32XX_CPU_H
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#define _LPC32XX_CPU_H
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/* LPC32XX Memory map */
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/* AHB physical base addresses */
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#define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */
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#define SSP0_BASE 0x20084000 /* SSP0 registers base */
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#define SD_CARD_BASE 0x20098000 /* SD card interface registers base */
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#define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */
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#define DMA_BASE 0x31000000 /* DMA controller registers base */
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#define USB_BASE 0x31020000 /* USB registers base */
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#define LCD_BASE 0x31040000 /* LCD registers base */
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#define ETHERNET_BASE 0x31060000 /* Ethernet registers base */
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#define EMC_BASE 0x31080000 /* EMC configuration registers base */
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/* FAB peripherals base addresses */
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#define CLK_PM_BASE 0x40004000 /* System control registers base */
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#define HS_UART1_BASE 0x40014000 /* High speed UART 1 registers base */
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#define HS_UART2_BASE 0x40018000 /* High speed UART 2 registers base */
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#define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */
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#define RTC_BASE 0x40024000 /* RTC registers base */
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#define GPIO_BASE 0x40028000 /* GPIO registers base */
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#define MUX_BASE 0x40028000 /* MUX registers base */
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#define WDT_BASE 0x4003C000 /* Watchdog timer registers base */
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#define TIMER0_BASE 0x40044000 /* Timer0 registers base */
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#define TIMER1_BASE 0x4004C000 /* Timer1 registers base */
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#define UART_CTRL_BASE 0x40054000 /* UART control regsisters base */
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/* APB peripherals base addresses */
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#define UART3_BASE 0x40080000 /* UART 3 registers base */
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#define UART4_BASE 0x40088000 /* UART 4 registers base */
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#define UART5_BASE 0x40090000 /* UART 5 registers base */
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#define UART6_BASE 0x40098000 /* UART 6 registers base */
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#define I2C1_BASE 0x400A0000 /* I2C 1 registers base */
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#define I2C2_BASE 0x400A8000 /* I2C 2 registers base */
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/* External SDRAM Memory Bank base addresses */
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#define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */
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#define EMC_DYCS1_BASE 0xA0000000 /* SDRAM DYCS1 base address */
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/* External Static Memory Bank base addresses */
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#define EMC_CS0_BASE 0xE0000000
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#define EMC_CS1_BASE 0xE1000000
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#define EMC_CS2_BASE 0xE2000000
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#define EMC_CS3_BASE 0xE3000000
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#endif /* _LPC32XX_CPU_H */
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