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https://github.com/brain-hackers/u-boot-brain
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550e3dc090
LS102xA is an ARMv7 implementation. This patch is to add basic support for LS1021AQDS board. One DDR controller DUART1 is used as the console For the detail board information, please refer to README. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
50 lines
1.4 KiB
C
50 lines
1.4 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DDR_H__
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#define __DDR_H__
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 rank_gb;
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u32 clk_adjust;
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u32 wrlvl_start;
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u32 wrlvl_ctl_2;
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u32 wrlvl_ctl_3;
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u32 cpo_override;
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u32 write_data_delay;
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u32 force_2t;
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};
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/*
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* These tables contain all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*/
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static const struct board_specific_parameters udimm0[] = {
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/*
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* memory controller 0
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
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*/
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{1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
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{1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
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{1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
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{1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
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{2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
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{2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
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{2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
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{2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
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{2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
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{}
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};
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static const struct board_specific_parameters *udimms[] = {
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udimm0,
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};
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#endif
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