u-boot-brain/arch/arm/cpu/armv7/at91/cpu.c
Wu, Josh d337a09c30 ARMv7: at91: enable ICache and DCache.
For at91 armv7 SoC (SAMA5D3x), only LCD and macb used DMA.
Now as the lcd and macb driver already support dcache. So we can
enable dcache now.

Also we can enable icache without any problem.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-06-14 18:07:03 +02:00

77 lines
1.6 KiB
C

/*
* (C) Copyright 2010
* Reinhard Meyer, reinhard.meyer@emk-elektronik.de
* (C) Copyright 2009
* Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* (C) Copyright 2013
* Bo Shen <voice.shen@atmel.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_dbu.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_pit.h>
#include <asm/arch/at91_gpbr.h>
#include <asm/arch/clk.h>
#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
#define CONFIG_SYS_AT91_MAIN_CLOCK 0
#endif
int arch_cpu_init(void)
{
return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
}
void arch_preboot_os(void)
{
ulong cpiv;
at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
/*
* Disable PITC
* Add 0x1000 to current counter to stop it faster
* without waiting for wrapping back to 0
*/
writel(cpiv + 0x1000, &pit->mr);
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
char buf[32];
printf("CPU: %s\n", get_cpu_name());
printf("Crystal frequency: %8s MHz\n",
strmhz(buf, get_main_clk_rate()));
printf("CPU clock : %8s MHz\n",
strmhz(buf, get_cpu_clk_rate()));
printf("Master clock : %8s MHz\n",
strmhz(buf, get_mck_clk_rate()));
return 0;
}
#endif
void enable_caches(void)
{
icache_enable();
dcache_enable();
}
unsigned int get_chip_id(void)
{
return readl(ATMEL_BASE_DBGU + AT91_DBU_CIDR) & ~AT91_DBU_CIDR_MASK;
}
unsigned int get_extension_chip_id(void)
{
return readl(ATMEL_BASE_DBGU + AT91_DBU_EXID);
}